[coreboot-gerrit] Change in coreboot[master]: nb/intel/haswell: Add Crystal Well PCI IDs

[Iru Cai (vimacs) (Code Review)]

Hello Iru Cai,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/41658

to review the following change.

Change subject: nb/intel/haswell: Add Crystal Well PCI IDs
......................................................................

nb/intel/haswell: Add Crystal Well PCI IDs

From a log of a machine using Crystal Well CPU [1], Crystal Well CPUs
use some new PCI IDs. Without this patch, the Crystal Well northbridge
cannot be initialized in ramstage, thus the machine cannot boot. The
PCI IDs of Crystal Well related devices can be found online [2].

Not tested on real hardware yet.

[1] https://mail.coreboot.org/hyperkitty/list/[e-mail]/thread/DNHLQ...
[2] https://pci-ids.ucw.cz/read/PC/8086

Change-Id: Icfe55323fd06187148c788ebfa7b679b6944e4f3
Signed-off-by: Iru Cai 
---
M src/northbridge/intel/haswell/minihd.c
M src/northbridge/intel/haswell/northbridge.c
M src/northbridge/intel/haswell/pcie.c
3 files changed, 6 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/41658/1

diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c
index f8a16e2..0a0a861 100644
--- a/src/northbridge/intel/haswell/minihd.c
+++ b/src/northbridge/intel/haswell/minihd.c
@@ -97,7 +97,7 @@
    .ops_pci		= &minihd_pci_ops,
 };

-static const unsigned short pci_device_ids[] = { 0x0a0c, 0x0c0c, 0 };
+static const unsigned short pci_device_ids[] = { 0x0a0c, 0x0c0c, 0x0d0c, 0 };

static const struct pci_driver haswell_minihd __pci_driver = {
    .ops	 = &minihd_ops,
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index a728e0e..c1bc245 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -466,6 +466,7 @@
    0x0c04, /* Mobile */
    0x0a04, /* ULT */
    0x0c08, /* Server */
+	0x0d00, 0x0d04, /* Crystal Well */
    0
 };

diff --git a/src/northbridge/intel/haswell/pcie.c b/src/northbridge/intel/haswell/pcie.c
index 74f11dd..73e909e 100644
--- a/src/northbridge/intel/haswell/pcie.c
+++ b/src/northbridge/intel/haswell/pcie.c
@@ -65,7 +65,10 @@
 #endif
 };

-static const unsigned short pci_device_ids[] = { 0x0c01, 0x0c05, 0x0c09, 0x0c0d, 0 };
+static const unsigned short pci_device_ids[] = {
+	0x0c01, 0x0c05, 0x0c09, 0x0c0d,
+	0x0d01, 0x0d05, 0x0d09, /* Crystal Well */
+	0 };

static const struct pci_driver pch_pcie __pci_driver = {
    .ops		= &device_ops,