[coreboot-gerrit] Change in coreboot[master]: soc/intel/broadwell: Drop unnecessary `sa_dev`

[Hung-Te Lin (Code Review)]

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46982 )

Change subject: soc/intel/broadwell: Drop unnecessary `sa_dev`
......................................................................

soc/intel/broadwell: Drop unnecessary `sa_dev`

Change-Id: Icc70adb0c3527a082622fd0ab70888e6cdf6b0ed
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46982
Reviewed-by: Christian Walter 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/broadwell/northbridge.c
1 file changed, 1 insertion(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Christian Walter: Looks good to me, approved

diff --git a/src/soc/intel/broadwell/northbridge.c b/src/soc/intel/broadwell/northbridge.c
index b9aeb38..5f7d43b 100644
--- a/src/soc/intel/broadwell/northbridge.c
+++ b/src/soc/intel/broadwell/northbridge.c
@@ -280,7 +280,6 @@
    uint64_t mc_values[NUM_MAP_ENTRIES];
    unsigned long dpr_size = 0;
    u32 dpr_reg;
-	struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);

/* Read in the MAP registers and report their values. */
    mc_read_map_entries(dev, &mc_values[0]);
@@ -292,7 +291,7 @@
     * the DPR register reports the TOP of the region, which is the same
     * as TSEG base.  The region size is reported in MiB in bits 11:4.
     */
-	dpr_reg = pci_read_config32(sa_dev, DPR);
+	dpr_reg = pci_read_config32(dev, DPR);
    if (dpr_reg & DPR_EPM) {
    	dpr_size = (dpr_reg & DPR_SIZE_MASK) << 16;
    	printk(BIOS_INFO, "DPR SIZE: 0x%lx\n", dpr_size);