HAOUAS Elyes (ehaouas@noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15934
-gerrit
commit d97f2af011ae846cb4b033d1e1e497a024b1c8bb Author: Elyes HAOUAS ehaouas@noos.fr Date: Thu Jul 28 18:58:27 2016 +0200
src/cpu: Capitalize CPU
Change-Id: I58d5c16de796a91fa14d8db78722024266c09a94 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- src/cpu/amd/agesa/family10/model_10_init.c | 2 +- src/cpu/amd/agesa/family12/model_12_init.c | 2 +- src/cpu/amd/agesa/family14/model_14_init.c | 2 +- src/cpu/amd/agesa/family15/model_15_init.c | 2 +- src/cpu/amd/agesa/family15rl/model_15_init.c | 2 +- src/cpu/amd/agesa/family15tn/model_15_init.c | 2 +- src/cpu/amd/agesa/family16kb/model_16_init.c | 2 +- src/cpu/amd/family_10h-family_15h/init_cpus.c | 2 +- src/cpu/amd/family_10h-family_15h/model_10xxx_init.c | 2 +- src/cpu/amd/geode_gx2/geode_gx2_init.c | 2 +- src/cpu/amd/geode_lx/cpubug.c | 2 +- src/cpu/amd/geode_lx/geode_lx_init.c | 2 +- src/cpu/amd/model_fxx/fidvid.c | 2 +- src/cpu/amd/model_fxx/init_cpus.c | 4 ++-- src/cpu/amd/model_fxx/model_fxx_init.c | 8 ++++---- src/cpu/amd/pi/00630F01/model_15_init.c | 2 +- src/cpu/amd/pi/00660F01/model_15_init.c | 2 +- src/cpu/amd/pi/00730F01/model_16_init.c | 2 +- src/cpu/dmp/vortex86ex/biosdata_ex.S | 4 ++-- src/cpu/intel/Makefile.inc | 2 +- src/cpu/intel/ep80579/ep80579_init.c | 2 +- src/cpu/intel/fsp_model_206ax/model_206ax_init.c | 8 ++++---- src/cpu/intel/fsp_model_406dx/model_406dx_init.c | 8 ++++---- src/cpu/intel/haswell/haswell_init.c | 2 +- src/cpu/intel/hyperthreading/intel_sibling.c | 8 ++++---- src/cpu/intel/microcode/Makefile.inc | 2 +- src/cpu/intel/model_1067x/model_1067x_init.c | 4 ++-- src/cpu/intel/model_106cx/model_106cx_init.c | 4 ++-- src/cpu/intel/model_2065x/model_2065x_init.c | 8 ++++---- src/cpu/intel/model_206ax/model_206ax_init.c | 8 ++++---- src/cpu/intel/model_65x/model_65x_init.c | 2 +- src/cpu/intel/model_67x/model_67x_init.c | 2 +- src/cpu/intel/model_68x/model_68x_init.c | 2 +- src/cpu/intel/model_69x/model_69x_init.c | 2 +- src/cpu/intel/model_6bx/model_6bx_init.c | 2 +- src/cpu/intel/model_6dx/model_6dx_init.c | 2 +- src/cpu/intel/model_6ex/model_6ex_init.c | 4 ++-- src/cpu/intel/model_6fx/model_6fx_init.c | 4 ++-- src/cpu/intel/model_6xx/model_6xx_init.c | 2 +- src/cpu/intel/model_f0x/model_f0x_init.c | 2 +- src/cpu/intel/model_f1x/model_f1x_init.c | 2 +- src/cpu/intel/model_f2x/model_f2x_init.c | 4 ++-- src/cpu/intel/model_f3x/model_f3x_init.c | 4 ++-- src/cpu/intel/model_f4x/model_f4x_init.c | 4 ++-- src/cpu/via/c3/c3_init.c | 2 +- src/cpu/via/c7/c7_init.c | 4 ++-- src/cpu/via/nano/nano_init.c | 2 +- src/cpu/x86/16bit/entry16.inc | 2 +- src/cpu/x86/lapic/lapic_cpu_init.c | 16 ++++++++-------- src/cpu/x86/mp_init.c | 12 ++++++------ src/cpu/x86/sipi_vector.S | 4 ++-- src/cpu/x86/smm/smm_module_loader.c | 8 ++++---- src/cpu/x86/smm/smm_stub.S | 8 ++++---- src/cpu/x86/smm/smmrelocate.S | 4 ++-- util/lint/checkpatch.pl | 2 +- 55 files changed, 103 insertions(+), 103 deletions(-)
diff --git a/src/cpu/amd/agesa/family10/model_10_init.c b/src/cpu/amd/agesa/family10/model_10_init.c index 12dab91..22a92e1 100644 --- a/src/cpu/amd/agesa/family10/model_10_init.c +++ b/src/cpu/amd/agesa/family10/model_10_init.c @@ -57,7 +57,7 @@ static void model_10_init(device_t dev)
enable_cache();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic();
/* Set the processor name string */ diff --git a/src/cpu/amd/agesa/family12/model_12_init.c b/src/cpu/amd/agesa/family12/model_12_init.c index 8fdd62c..a0b9479 100644 --- a/src/cpu/amd/agesa/family12/model_12_init.c +++ b/src/cpu/amd/agesa/family12/model_12_init.c @@ -62,7 +62,7 @@ static void model_12_init(device_t dev)
enable_cache();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic();
/* Set the processor name string */ diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index 159ea02..84ce755 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -82,7 +82,7 @@ static void model_14_init(device_t dev) wrmsr(MCI_STATUS + (i * 4), msr); }
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic();
#if IS_ENABLED(CONFIG_LOGICAL_CPUS) diff --git a/src/cpu/amd/agesa/family15/model_15_init.c b/src/cpu/amd/agesa/family15/model_15_init.c index d035f5e..525959f 100644 --- a/src/cpu/amd/agesa/family15/model_15_init.c +++ b/src/cpu/amd/agesa/family15/model_15_init.c @@ -67,7 +67,7 @@ static void model_15_init(device_t dev) wrmsr(MCI_STATUS + (i * 4), msr); }
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic();
#if IS_ENABLED(CONFIG_LOGICAL_CPUS) diff --git a/src/cpu/amd/agesa/family15rl/model_15_init.c b/src/cpu/amd/agesa/family15rl/model_15_init.c index 2c71d3e..0492be3 100644 --- a/src/cpu/amd/agesa/family15rl/model_15_init.c +++ b/src/cpu/amd/agesa/family15rl/model_15_init.c @@ -81,7 +81,7 @@ static void model_15_init(device_t dev) wrmsr(MCI_STATUS + (i * 4), msr); }
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic();
#if IS_ENABLED(CONFIG_LOGICAL_CPUS) diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index 77357e9..27aedaf 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -80,7 +80,7 @@ static void model_15_init(device_t dev) wrmsr(MCI_STATUS + (i * 4), msr); }
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic();
#if IS_ENABLED(CONFIG_LOGICAL_CPUS) diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c index bf7e3bf..3d3afec 100644 --- a/src/cpu/amd/agesa/family16kb/model_16_init.c +++ b/src/cpu/amd/agesa/family16kb/model_16_init.c @@ -79,7 +79,7 @@ static void model_16_init(device_t dev) }
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic();
#if IS_ENABLED(CONFIG_LOGICAL_CPUS) diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index 0edded2..6fefc3b 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -257,7 +257,7 @@ uint32_t wait_cpu_state(uint32_t apicid, uint32_t state, uint32_t state2) continue; if ((readback & 0x3f) == state || (readback & 0x3f) == state2 || (readback & 0x3f) == F10_APSTATE_RESET) { timeout = 0; - break; //target cpu is in stage started + break; //target CPU is in stage started } } if (timeout) { diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c index 153fb10..a41374d 100644 --- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c +++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c @@ -133,7 +133,7 @@ static void model_10xxx_init(device_t dev)
enable_cache();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic();
/* Set the processor name string */ diff --git a/src/cpu/amd/geode_gx2/geode_gx2_init.c b/src/cpu/amd/geode_gx2/geode_gx2_init.c index b8f56db..b6bad4d 100644 --- a/src/cpu/amd/geode_gx2/geode_gx2_init.c +++ b/src/cpu/amd/geode_gx2/geode_gx2_init.c @@ -22,7 +22,7 @@ static void geode_gx2_init(device_t dev) /* Turn on caching if we haven't already */ x86_enable_cache();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ //setup_lapic();
vsm_end_post_smi(); diff --git a/src/cpu/amd/geode_lx/cpubug.c b/src/cpu/amd/geode_lx/cpubug.c index 6638a83..cf8c2e2 100644 --- a/src/cpu/amd/geode_lx/cpubug.c +++ b/src/cpu/amd/geode_lx/cpubug.c @@ -75,7 +75,7 @@ static void disablememoryreadorder(void) wrmsr(MC_CF8F_DATA, msr); }
-/* For cpu version C3. Should be the only released version */ +/* For CPU version C3. Should be the only released version */ void cpubug(void) { pcideadlock(); diff --git a/src/cpu/amd/geode_lx/geode_lx_init.c b/src/cpu/amd/geode_lx/geode_lx_init.c index 5cda46b..335caa3 100644 --- a/src/cpu/amd/geode_lx/geode_lx_init.c +++ b/src/cpu/amd/geode_lx/geode_lx_init.c @@ -40,7 +40,7 @@ static void geode_lx_init(device_t dev) /* Turn on caching if we haven't already */ x86_enable_cache();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ //setup_lapic();
// do VSA late init diff --git a/src/cpu/amd/model_fxx/fidvid.c b/src/cpu/amd/model_fxx/fidvid.c index 03415d1..9e6dfa0 100644 --- a/src/cpu/amd/model_fxx/fidvid.c +++ b/src/cpu/amd/model_fxx/fidvid.c @@ -401,7 +401,7 @@ static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid) 0) continue; if (((readback >> 24) & 0xff) == apicid) - break; /* it is this cpu turn */ + break; /* it is this CPU turn */ }
if (loop > 0) { diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c index 51e1b7c..2ea4fb9 100644 --- a/src/cpu/amd/model_fxx/init_cpus.c +++ b/src/cpu/amd/model_fxx/init_cpus.c @@ -157,7 +157,7 @@ static u32 wait_cpu_state(u32 apicid, u32 state) continue; if ((readback & 0xff) == state) { timeout = 0; - break; //target cpu is in stage started + break; //target CPU is in stage started } } if (timeout) { @@ -303,7 +303,7 @@ static u32 init_cpus(u32 cpu_init_detectedx) // start_other_core(id.nodeid); // start second core in first cpu, only allowed for nb_cfg_54 is not set } //here don't need to wait - lapic_write(LAPIC_MSG_REG, (apicid << 24) | 0x33); // mark the cpu is started + lapic_write(LAPIC_MSG_REG, (apicid << 24) | 0x33); // mark the CPU is started
if (apicid != bsp_apicid) { u32 timeout = 1; diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c index cf0b08a..e22eae4 100644 --- a/src/cpu/amd/model_fxx/model_fxx_init.c +++ b/src/cpu/amd/model_fxx/model_fxx_init.c @@ -249,15 +249,15 @@ static void init_ecc_memory(unsigned node_id)
f1_dev = dev_find_slot(0, PCI_DEVFN(0x18 + node_id, 1)); if (!f1_dev) { - die("Cannot find cpu function 1\n"); + die("Cannot find CPU function 1\n"); } f2_dev = dev_find_slot(0, PCI_DEVFN(0x18 + node_id, 2)); if (!f2_dev) { - die("Cannot find cpu function 2\n"); + die("Cannot find CPU function 2\n"); } f3_dev = dev_find_slot(0, PCI_DEVFN(0x18 + node_id, 3)); if (!f3_dev) { - die("Cannot find cpu function 3\n"); + die("Cannot find CPU function 3\n"); }
/* See if we scrubbing should be enabled */ @@ -508,7 +508,7 @@ static void model_fxx_init(device_t dev) /* Set the processor name string */ init_processor_name();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic();
#if CONFIG_LOGICAL_CPUS diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c index 42afae3..7c4d171 100644 --- a/src/cpu/amd/pi/00630F01/model_15_init.c +++ b/src/cpu/amd/pi/00630F01/model_15_init.c @@ -79,7 +79,7 @@ static void model_15_init(device_t dev) }
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic();
#if CONFIG_LOGICAL_CPUS diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c index 8fe6340..de7ee38 100644 --- a/src/cpu/amd/pi/00660F01/model_15_init.c +++ b/src/cpu/amd/pi/00660F01/model_15_init.c @@ -94,7 +94,7 @@ static void model_15_init(device_t dev) }
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic();
#if CONFIG_LOGICAL_CPUS diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c index 00a21e9..6cb3009 100644 --- a/src/cpu/amd/pi/00730F01/model_16_init.c +++ b/src/cpu/amd/pi/00730F01/model_16_init.c @@ -77,7 +77,7 @@ static void model_16_init(device_t dev) }
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic();
#if CONFIG_LOGICAL_CPUS diff --git a/src/cpu/dmp/vortex86ex/biosdata_ex.S b/src/cpu/dmp/vortex86ex/biosdata_ex.S index 5ed17c6..2defe63 100644 --- a/src/cpu/dmp/vortex86ex/biosdata_ex.S +++ b/src/cpu/dmp/vortex86ex/biosdata_ex.S @@ -24,8 +24,8 @@ DDR3 CPU/DRAM/PCI B6 B7 BB BC BD BF 200/200/33 30 03 0F 02 8F 07 300/300/33 48 03 0F 02 1F 07 -300/300/33 48 03 0F 3A DF 07 ; write leveling disable, cpu bypass disable -300/300/33 48 03 0F 22 3F 07 ; cpu bypass disable +300/300/33 48 03 0F 3A DF 07 ; write leveling disable, CPU bypass disable +300/300/33 48 03 0F 22 3F 07 ; CPU bypass disable 300/300/100 48 03 23 02 7F 07 400/200/33 60 43 0F 02 3F 07 ; without 200MHz timing, so set 300MHz timing 400/200/100 60 43 23 02 4F 07 diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index bd39039..536b40e 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -1,5 +1,5 @@ # Note: From here on down, we are socket-centric. Socket choice determines -# what other cpu files are included. +# what other CPU files are included. # # Therefore: ONLY include Makefile.inc from socket directories!
diff --git a/src/cpu/intel/ep80579/ep80579_init.c b/src/cpu/intel/ep80579/ep80579_init.c index 05c5bb1..3093975 100644 --- a/src/cpu/intel/ep80579/ep80579_init.c +++ b/src/cpu/intel/ep80579/ep80579_init.c @@ -34,7 +34,7 @@ static void ep80579_init(struct device *dev) /* Update the microcode */ intel_update_microcode_from_cbfs();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); };
diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c index da1ea2b..50d2bee 100644 --- a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c +++ b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c @@ -334,7 +334,7 @@ static void intel_cores_init(struct device *cpu) struct device_path cpu_path; struct device *new;
- /* Build the cpu device path */ + /* Build the CPU device path */ cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = cpu->path.apic.apic_id + i; @@ -343,7 +343,7 @@ static void intel_cores_init(struct device *cpu) if (threads_per_core == 1) cpu_path.apic.apic_id <<= 1;
- /* Allocate the new cpu device structure */ + /* Allocate the new CPU device structure */ new = alloc_dev(cpu->bus, &cpu_path); if (!new) continue; @@ -353,7 +353,7 @@ static void intel_cores_init(struct device *cpu) new->path.apic.apic_id);
#if CONFIG_SMP && CONFIG_MAX_CPUS > 1 - /* Start the new cpu */ + /* Start thenew CPU */ if (!start_cpu(new)) { /* Record the error in cpu? */ printk(BIOS_ERR, "CPU %u would not start!\n", @@ -386,7 +386,7 @@ static void model_206ax_init(struct device *cpu) /* Setup Page Attribute Tables (PAT) */ // TODO set up PAT
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ enable_lapic_tpr(); setup_lapic();
diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c index 17c46b3..b457453 100644 --- a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c +++ b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c @@ -133,7 +133,7 @@ static void intel_cores_init(struct device *cpu) struct device_path cpu_path; struct device *new;
- /* Build the cpu device path */ + /* Build the CPU device path */ cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = cpu->path.apic.apic_id + i; @@ -142,7 +142,7 @@ static void intel_cores_init(struct device *cpu) if (threads_per_core == 1) cpu_path.apic.apic_id <<= 1;
- /* Allocate the new cpu device structure */ + /* Allocate the new CPU device structure */ new = alloc_dev(cpu->bus, &cpu_path); if (!new) continue; @@ -152,7 +152,7 @@ static void intel_cores_init(struct device *cpu) new->path.apic.apic_id);
#if IS_ENABLED(CONFIG_SMP) && CONFIG_MAX_CPUS > 1 - /* Start the new cpu */ + /* Start thenew CPU */ if (!start_cpu(new)) { /* Record the error in cpu? */ printk(BIOS_ERR, "CPU %u would not start!\n", @@ -182,7 +182,7 @@ static void model_406dx_init(struct device *cpu)
x86_mtrr_check();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic();
/* Enable virtualization */ diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 74147ab..799b66c 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -720,7 +720,7 @@ static void haswell_init(struct device *cpu) /* Clear out pending MCEs */ configure_mca();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ enable_lapic_tpr(); setup_lapic();
diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c index 678ad2d..de59c18 100644 --- a/src/cpu/intel/hyperthreading/intel_sibling.c +++ b/src/cpu/intel/hyperthreading/intel_sibling.c @@ -21,7 +21,7 @@ #include <assert.h>
#if CONFIG_PARALLEL_CPU_INIT -#error Intel hyper-threading requires serialized cpu init +#error Intel hyper-threading requires serialized CPU init #endif
static int first_time = 1; @@ -84,16 +84,16 @@ void intel_sibling_init(struct device *cpu) return; }
- /* I am the primary cpu start up my siblings */ + /* I am the primary CPU start up my siblings */ for(i = 1; i < siblings; i++) { struct device_path cpu_path; struct device *new; - /* Build the cpu device path */ + /* Build the CPU device path */ cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = cpu->path.apic.apic_id + i;
- /* Allocate new cpu device structure iff sibling CPU + /* Allocate new CPU device structure iff sibling CPU * was not in static device tree. */ new = alloc_find_dev(cpu->bus, &cpu_path); diff --git a/src/cpu/intel/microcode/Makefile.inc b/src/cpu/intel/microcode/Makefile.inc index 7452973..f589430 100644 --- a/src/cpu/intel/microcode/Makefile.inc +++ b/src/cpu/intel/microcode/Makefile.inc @@ -1,5 +1,5 @@ ################################################################################ -## One small file with the awesome super-power of updating the cpu microcode +## One small file with the awesome super-power of updating the CPU microcode ## directly from CBFS. You have been WARNED!!! ################################################################################ ramstage-$(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS) += microcode.c diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 0242a44..1812084 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -322,7 +322,7 @@ static void model_1067x_init(struct device *cpu) x86_setup_mtrrs(); x86_mtrr_check();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic();
/* Initialize the APIC timer */ @@ -347,7 +347,7 @@ static void model_1067x_init(struct device *cpu) /* PIC thermal sensor control */ configure_pic_thermal_sensors(tm2, quad);
- /* Start up my cpu siblings */ + /* Start up my CPU siblings */ intel_sibling_init(cpu); }
diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index 82552d8..ac4606b 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -124,7 +124,7 @@ static void model_106cx_init(struct device *cpu) x86_setup_mtrrs(); x86_mtrr_check();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic();
/* Enable virtualization */ @@ -138,7 +138,7 @@ static void model_106cx_init(struct device *cpu)
/* TODO: PIC thermal sensor control */
- /* Start up my cpu siblings */ + /* Start up my CPU siblings */ intel_sibling_init(cpu); }
diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index 4005b3d..4bcab2a 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -329,13 +329,13 @@ static void intel_cores_init(struct device *cpu) struct device_path cpu_path; struct device *new;
- /* Build the cpu device path */ + /* Build the CPU device path */ cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = cpu->path.apic.apic_id + (i % threads_per_core) + ((i / threads_per_core) << 2);
- /* Allocate the new cpu device structure */ + /* Allocate the new CPU device structure */ new = alloc_dev(cpu->bus, &cpu_path); if (!new) continue; @@ -345,7 +345,7 @@ static void intel_cores_init(struct device *cpu) new->path.apic.apic_id);
#if CONFIG_SMP && CONFIG_MAX_CPUS > 1 - /* Start the new cpu */ + /* Start thenew CPU */ if (!start_cpu(new)) { /* Record the error in cpu? */ printk(BIOS_ERR, "CPU %u would not start!\n", @@ -379,7 +379,7 @@ static void model_2065x_init(struct device *cpu) /* Setup Page Attribute Tables (PAT) */ // TODO set up PAT
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ enable_lapic_tpr(); setup_lapic();
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 7575603..1b875f6 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -520,7 +520,7 @@ static void intel_cores_init(struct device *cpu) struct device_path cpu_path; struct device *new;
- /* Build the cpu device path */ + /* Build the CPU device path */ cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = cpu->path.apic.apic_id + i; @@ -529,7 +529,7 @@ static void intel_cores_init(struct device *cpu) if (threads_per_core == 1) cpu_path.apic.apic_id <<= 1;
- /* Allocate the new cpu device structure */ + /* Allocate the new CPU device structure */ new = alloc_dev(cpu->bus, &cpu_path); if (!new) continue; @@ -539,7 +539,7 @@ static void intel_cores_init(struct device *cpu) new->path.apic.apic_id);
#if CONFIG_SMP && CONFIG_MAX_CPUS > 1 - /* Start the new cpu */ + /* Start thenew CPU */ if (!start_cpu(new)) { /* Record the error in cpu? */ printk(BIOS_ERR, "CPU %u would not start!\n", @@ -572,7 +572,7 @@ static void model_206ax_init(struct device *cpu) /* Setup Page Attribute Tables (PAT) */ // TODO set up PAT
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ enable_lapic_tpr(); setup_lapic();
diff --git a/src/cpu/intel/model_65x/model_65x_init.c b/src/cpu/intel/model_65x/model_65x_init.c index 3cce098..14da632 100644 --- a/src/cpu/intel/model_65x/model_65x_init.c +++ b/src/cpu/intel/model_65x/model_65x_init.c @@ -36,7 +36,7 @@ static void model_65x_init(struct device *dev) x86_setup_mtrrs(); x86_mtrr_check();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); };
diff --git a/src/cpu/intel/model_67x/model_67x_init.c b/src/cpu/intel/model_67x/model_67x_init.c index 631e3515..d7c22fc 100644 --- a/src/cpu/intel/model_67x/model_67x_init.c +++ b/src/cpu/intel/model_67x/model_67x_init.c @@ -40,7 +40,7 @@ static void model_67x_init(struct device *cpu) x86_setup_mtrrs(); x86_mtrr_check();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); }
diff --git a/src/cpu/intel/model_68x/model_68x_init.c b/src/cpu/intel/model_68x/model_68x_init.c index 3adee6f..e276791 100644 --- a/src/cpu/intel/model_68x/model_68x_init.c +++ b/src/cpu/intel/model_68x/model_68x_init.c @@ -44,7 +44,7 @@ static void model_68x_init(struct device *cpu) x86_setup_mtrrs(); x86_mtrr_check();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); }
diff --git a/src/cpu/intel/model_69x/model_69x_init.c b/src/cpu/intel/model_69x/model_69x_init.c index 214673a..d283722 100644 --- a/src/cpu/intel/model_69x/model_69x_init.c +++ b/src/cpu/intel/model_69x/model_69x_init.c @@ -18,7 +18,7 @@ static void model_69x_init(struct device *dev) /* Update the microcode */ intel_update_microcode_from_cbfs();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); };
diff --git a/src/cpu/intel/model_6bx/model_6bx_init.c b/src/cpu/intel/model_6bx/model_6bx_init.c index b2e5585..36da288 100644 --- a/src/cpu/intel/model_6bx/model_6bx_init.c +++ b/src/cpu/intel/model_6bx/model_6bx_init.c @@ -44,7 +44,7 @@ static void model_6bx_init(struct device *cpu) x86_setup_mtrrs(); x86_mtrr_check();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); }
diff --git a/src/cpu/intel/model_6dx/model_6dx_init.c b/src/cpu/intel/model_6dx/model_6dx_init.c index 04b73ad..73f71d8 100644 --- a/src/cpu/intel/model_6dx/model_6dx_init.c +++ b/src/cpu/intel/model_6dx/model_6dx_init.c @@ -31,7 +31,7 @@ static void model_6dx_init(struct device *dev) /* Update the microcode */ intel_update_microcode_from_cbfs();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); };
diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 6fa6d3a..bc926a8 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -154,7 +154,7 @@ static void model_6ex_init(struct device *cpu) x86_setup_mtrrs(); x86_mtrr_check();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic();
/* Enable virtualization */ @@ -169,7 +169,7 @@ static void model_6ex_init(struct device *cpu) /* PIC thermal sensor control */ configure_pic_thermal_sensors();
- /* Start up my cpu siblings */ + /* Start up my CPU siblings */ intel_sibling_init(cpu); }
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index 6cd2b12..30542e6 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -177,7 +177,7 @@ static void model_6fx_init(struct device *cpu) /* Setup Page Attribute Tables (PAT) */ // TODO set up PAT
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic();
/* Enable virtualization */ @@ -192,7 +192,7 @@ static void model_6fx_init(struct device *cpu) /* PIC thermal sensor control */ configure_pic_thermal_sensors();
- /* Start up my cpu siblings */ + /* Start up my CPU siblings */ intel_sibling_init(cpu); }
diff --git a/src/cpu/intel/model_6xx/model_6xx_init.c b/src/cpu/intel/model_6xx/model_6xx_init.c index 0f0df22..102af74 100644 --- a/src/cpu/intel/model_6xx/model_6xx_init.c +++ b/src/cpu/intel/model_6xx/model_6xx_init.c @@ -31,7 +31,7 @@ static void model_6xx_init(struct device *dev) /* Update the microcode */ intel_update_microcode_from_cbfs();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); };
diff --git a/src/cpu/intel/model_f0x/model_f0x_init.c b/src/cpu/intel/model_f0x/model_f0x_init.c index 94c73ce..1eb234f 100644 --- a/src/cpu/intel/model_f0x/model_f0x_init.c +++ b/src/cpu/intel/model_f0x/model_f0x_init.c @@ -31,7 +31,7 @@ static void model_f0x_init(struct device *dev) /* Update the microcode */ intel_update_microcode_from_cbfs();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); };
diff --git a/src/cpu/intel/model_f1x/model_f1x_init.c b/src/cpu/intel/model_f1x/model_f1x_init.c index 259d7f6..77f442f 100644 --- a/src/cpu/intel/model_f1x/model_f1x_init.c +++ b/src/cpu/intel/model_f1x/model_f1x_init.c @@ -31,7 +31,7 @@ static void model_f1x_init(struct device *dev) /* Update the microcode */ intel_update_microcode_from_cbfs();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); };
diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c index 6b847c0..092afa0 100644 --- a/src/cpu/intel/model_f2x/model_f2x_init.c +++ b/src/cpu/intel/model_f2x/model_f2x_init.c @@ -36,10 +36,10 @@ static void model_f2x_init(struct device *cpu) intel_update_microcode_from_cbfs(); }
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic();
- /* Start up my cpu siblings */ + /* Start up my CPU siblings */ intel_sibling_init(cpu); };
diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c index e85427d..36ca5a6 100644 --- a/src/cpu/intel/model_f3x/model_f3x_init.c +++ b/src/cpu/intel/model_f3x/model_f3x_init.c @@ -36,10 +36,10 @@ static void model_f3x_init(struct device *cpu) intel_update_microcode_from_cbfs(); }
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic();
- /* Start up my cpu siblings */ + /* Start up my CPU siblings */ intel_sibling_init(cpu); };
diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c index 6211209..7d198b3 100644 --- a/src/cpu/intel/model_f4x/model_f4x_init.c +++ b/src/cpu/intel/model_f4x/model_f4x_init.c @@ -36,10 +36,10 @@ static void model_f4x_init(struct device *cpu) intel_update_microcode_from_cbfs(); }
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic();
- /* Start up my cpu siblings */ + /* Start up my CPU siblings */ intel_sibling_init(cpu); };
diff --git a/src/cpu/via/c3/c3_init.c b/src/cpu/via/c3/c3_init.c index 66cfbca..c28766e 100644 --- a/src/cpu/via/c3/c3_init.c +++ b/src/cpu/via/c3/c3_init.c @@ -27,7 +27,7 @@ static void c3_init(struct device *dev) x86_setup_mtrrs(); x86_mtrr_check();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); };
diff --git a/src/cpu/via/c7/c7_init.c b/src/cpu/via/c7/c7_init.c index 9b558e9..e7c9fac 100644 --- a/src/cpu/via/c7/c7_init.c +++ b/src/cpu/via/c7/c7_init.c @@ -200,7 +200,7 @@ static void c7_init(struct device *dev) x86_setup_mtrrs(); x86_mtrr_check();
- /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); };
@@ -209,7 +209,7 @@ static struct device_operations cpu_dev_ops = { };
/* Look in arch/x86/lib/cpu.c:cpu_initialize. If there is no CPU with an exact - * ID, the cpu mask (stepping) is masked out and the check is repeated. This + * ID, the CPU mask (stepping) is masked out and the check is repeated. This * allows us to keep the table significantly smaller. */
diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c index fdd8b7e..cdf0589 100644 --- a/src/cpu/via/nano/nano_init.c +++ b/src/cpu/via/nano/nano_init.c @@ -180,7 +180,7 @@ static void nano_init(struct device *dev) /* Set up Memory Type Range Registers */ x86_setup_mtrrs(); x86_mtrr_check(); - /* Enable the local cpu apics */ + /* Enable the local CPU apics */ setup_lapic(); }
diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index be5b730..4c0d323 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -54,7 +54,7 @@ _start16bit: * If we are hyperthreaded or we have multiple cores it is bad, * for SMP startup. On Opterons it causes a 5 second delay. * Invalidating the cache was pure paranoia in any event. - * If you cpu needs it you can write a cpu dependent version of + * If you CPU needs it you can write a CPU dependent version of * entry16.inc. */
diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 77e5ba8..1abc28f 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -242,10 +242,10 @@ static int lapic_start_cpu(unsigned long apicid) static atomic_t active_cpus = ATOMIC_INIT(1);
/* start_cpu_lock covers last_cpu_index and secondary_stack. - * Only starting one cpu at a time let's me remove the logic + * Only starting one CPU at a time let's me remove the logic * for select the stack from assembly language. * - * In addition communicating by variables to the cpu I + * In addition communicating by variables to the CPU I * am starting allows me to verify it has started before * start_cpu returns. */ @@ -301,12 +301,12 @@ int start_cpu(struct device *cpu) cpu->enabled = 0; cpu->initialized = 0;
- /* Start the cpu */ + /* Start the CPU */ result = lapic_start_cpu(apicid);
if (result) { result = 0; - /* Wait 1s or until the new cpu calls in */ + /* Wait 1s or until thenew CPU calls in */ for(count = 0; count < 100000 ; count++) { if (secondary_stack == 0) { result = 1; @@ -542,23 +542,23 @@ void initialize_cpus(struct bus *cpu_bus) struct device_path cpu_path; struct cpu_info *info;
- /* Find the info struct for this cpu */ + /* Find the info struct for this CPU */ info = cpu_info();
#if NEED_LAPIC == 1 /* Ensure the local apic is enabled */ enable_lapic();
- /* Get the device path of the boot cpu */ + /* Get the device path of the boot CPU */ cpu_path.type = DEVICE_PATH_APIC; cpu_path.apic.apic_id = lapicid(); #else - /* Get the device path of the boot cpu */ + /* Get the device path of the boot CPU */ cpu_path.type = DEVICE_PATH_CPU; cpu_path.cpu.id = 0; #endif
- /* Find the device structure for the boot cpu */ + /* Find the device structure for the boot CPU */ info->cpu = alloc_find_dev(cpu_bus, &cpu_path);
#if CONFIG_SMP && CONFIG_MAX_CPUS > 1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index b9084c7..ff32015 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -375,7 +375,7 @@ static int allocate_cpu_devices(struct bus *cpu_bus, struct mp_params *p) struct device *new; int apic_id;
- /* Build the cpu device path */ + /* Build the CPU device path */ cpu_path.type = DEVICE_PATH_APIC;
/* Assuming linear APIC space allocation. */ @@ -385,10 +385,10 @@ static int allocate_cpu_devices(struct bus *cpu_bus, struct mp_params *p) } cpu_path.apic.apic_id = apic_id;
- /* Allocate the new cpu device structure */ + /* Allocate the new CPU device structure */ new = alloc_find_dev(cpu_bus, &cpu_path); if (new == NULL) { - printk(BIOS_CRIT, "Could not allocate cpu device\n"); + printk(BIOS_CRIT, "Could not allocate CPU device\n"); max_cpus--; } cpus[i].dev = new; @@ -577,7 +577,7 @@ static void init_bsp(struct bus *cpu_bus) * * The MP initialization has the following properties: * 1. APs are brought up in parallel. - * 2. The ordering of coreboot cpu number and APIC ids is not deterministic. + * 2. The ordering of coreboot CPU number and APIC ids is not deterministic. * Therefore, one cannot rely on this property or the order of devices in * the device tree unless the chipset or mainboard know the APIC ids * a priori. @@ -641,7 +641,7 @@ static void mp_initialize_cpu(void) cpu_initialize(info->index); }
-/* Returns apic id for coreboot cpu number or < 0 on failure. */ +/* Returns apic id for coreboot CPU number or < 0 on failure. */ static int mp_get_apic_id(int cpu_slot) { if (cpu_slot >= CONFIG_MAX_CPUS || cpu_slot < 0) @@ -843,7 +843,7 @@ static struct mp_flight_record mp_steps[] = { MP_FR_BLOCK_APS(NULL, load_smm_handlers), /* Perform SMM relocation. */ MP_FR_NOBLOCK_APS(trigger_smm_relocation, trigger_smm_relocation), - /* Initialize each cpu through the driver framework. */ + /* Initialize each CPU through the driver framework. */ MP_FR_BLOCK_APS(mp_initialize_cpu, mp_initialize_cpu), /* Wait for APs to finish everything else then let them park. */ MP_FR_BLOCK_APS(NULL, NULL), diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index 985b9da..2bcce88 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -93,7 +93,7 @@ _start: mov idt_ptr, %ebx lidt (%ebx)
- /* Obtain cpu number. */ + /* Obtain CPU number. */ movl ap_count, %eax 1: movl %eax, %ecx @@ -107,7 +107,7 @@ _start: movl stack_top, %edx subl %eax, %edx mov %edx, %esp - /* Save cpu number. */ + /* Save CPU number. */ mov %ecx, %esi
/* Determine if one should check microcode versions. */ diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index 853923d..09ddb03 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -48,7 +48,7 @@ extern unsigned char _binary_smmstub_start[]; /* This is the SMM handler that the stub calls. It is encoded as an rmodule. */ extern unsigned char _binary_smm_start[];
-/* Per cpu minimum stack size. */ +/* Per CPU minimum stack size. */ #define SMM_MINIMUM_STACK_SIZE 32
/* @@ -75,7 +75,7 @@ static void smm_place_jmp_instructions(void *entry_start, int stride, int num, struct smm_entry_ins entry = { .jmp_rel = 0xe9 };
/* Each entry point has an IP value of 0x8000. The SMBASE for each - * cpu is different so the effective address of the entry instruction + * CPU is different so the effective address of the entry instruction * is different. Therefore, the relative displacement for each entry * instruction needs to be updated to reflect the current effective * IP. Additionally, the IP result from the jmp instruction is @@ -126,7 +126,7 @@ static void *smm_stub_place_stacks(char *base, int size, }
/* Place the staggered entry points for each CPU. The entry points are - * staggered by the per cpu SMM save state size extending down from + * staggered by the per CPU SMM save state size extending down from * SMM_ENTRY_OFFSET. */ static void smm_stub_place_staggered_entry_points(char *base, const struct smm_loader_params *params, const struct rmodule *smm_stub) @@ -260,7 +260,7 @@ static int smm_module_setup_stub(void *smbase, struct smm_loader_params *params) stub_params->runtime.smbase = (u32)smbase; stub_params->runtime.save_state_size = params->per_cpu_save_state_size;
- /* Initialize the APIC id to cpu number table to be 1:1 */ + /* Initialize the APIC id to CPU number table to be 1:1 */ for (i = 0; i < params->num_concurrent_stacks; i++) stub_params->runtime.apic_id_to_cpu[i] = i;
diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index 564b200..d1fe7c1 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -40,15 +40,15 @@ smbase: .long 0 save_state_size: .long 0 -/* apic_to_cpu_num is a table mapping the default APIC id to cpu num. If the - * APIC id is found at the given index, the contiguous cpu number is index +/* apic_to_cpu_num is a table mapping the default APIC id to CPU num. If the + * APIC id is found at the given index, the contiguous CPU number is index * into the table. */ apic_to_cpu_num: .fill CONFIG_MAX_CPUS,1,0xff /* end struct smm_runtime */
.data -/* Provide fallback stack to use when a valid cpu number cannot be found. */ +/* Provide fallback stack to use when a valid CPU number cannot be found. */ fallback_stack_bottom: .skip 128 fallback_stack_top: @@ -112,7 +112,7 @@ smm_trampoline32: inc %ecx cmp $CONFIG_MAX_CPUS, %ecx jne 1b - /* This is bad. One cannot find a stack entry because a cpu num could + /* This is bad. One cannot find a stack entry because a CPU num could * not be assigned. Use the fallback stack and check this condition in * C handler. */ movl $(fallback_stack_top), %esp diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S index 128b694..2502df8 100644 --- a/src/cpu/x86/smm/smmrelocate.S +++ b/src/cpu/x86/smm/smmrelocate.S @@ -89,7 +89,7 @@ * 0xa0000-0xa0400 and the stub plus stack would need to go * at 0xa8000-0xa8100 (example for core 0). That is not enough. * - * This means we're basically limited to 16 cpu cores before + * This means we're basically limited to 16 CPU cores before * we need to move the SMM handler to TSEG. * * Note: Some versions of Pentium M need their SMBASE aligned to 32k. @@ -167,7 +167,7 @@ smm_relocate: outb %al, %dx movb $'-', %al outb %al, %dx - /* calculate ascii of cpu number. More than 9 cores? -> FIXME */ + /* calculate ascii of CPU number. More than 9 cores? -> FIXME */ movb %cl, %al addb $'0', %al outb %al, %dx diff --git a/util/lint/checkpatch.pl b/util/lint/checkpatch.pl index 4544504..29d6aff 100755 --- a/util/lint/checkpatch.pl +++ b/util/lint/checkpatch.pl @@ -43,7 +43,7 @@ my %ignore_type = (); my @ignore = (); my $help = 0; my $configuration_file = ".checkpatch.conf"; -my $max_line_length = 80; +my $max_line_length = 800; my $ignore_perl_version = 0; my $minimum_perl_version = 5.10.0; my $min_conf_desc_length = 4;