[coreboot-gerrit] Change in ...coreboot[master]: src/soc/intel/braswell/chip.c: Configure LPSS devices in correct mode

[Michał Żygowski (Code Review)]

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29284 )

Change subject: src/soc/intel/braswell/chip.c: Configure LPSS devices in correct mode
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Patch Set 3:
> Patch Set 3:
> > Patch Set 3:
> >
> > is the default PCI mode? (since you're not explicitly setting it)
> > what are the consequences of not passing the correct mode to FSP?
>
> Default can be PCI or ACPI, depending on values devicetree.cb.
> The child devices need to operate ACPI mode when the LPSS is operating in ACPI mode. For this reason the patch is uploaded.
>
> FSP MR2 does a check for ACPI mode and change the device mode. Supplying incorrect configuration will be corrected by FSP, but to be futher proof supply correct configuration to FSP.

By looking at the BSF file for Braswell FSP, the I2C and other LPSS devices are defined as Enable/Disable switches, so only binary configuration (0 or 1). Does it mean that that Intel did not document the ACPI mode as a 3rd option in the BSF and Integration Guide?