[coreboot-gerrit] Patch set updated for coreboot: 9cce482 nehalem/raminit: Don't touch clock generator in raminit.

[Vladimir Serbinenko]

Vladimir Serbinenko ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5265

-gerrit

commit 9cce482ca4b1160922fa5b6429d3afb867ace9f6
Author: Vladimir Serbinenko 
Date:   Wed Feb 19 22:07:12 2014 +0100

nehalem/raminit: Don't touch clock generator in raminit.

Clock generator is mobo-specific. Don't touch it in raminit.

Change-Id: Ie114696b7fb13b8daee8dd1393d43bc609e149b3
    Signed-off-by: Vladimir Serbinenko 
---
 src/mainboard/lenovo/x201/romstage.c    | 16 ++++++++++++++
 src/northbridge/intel/nehalem/raminit.c | 37 ++++++++++++---------------------
 src/northbridge/intel/nehalem/raminit.h |  1 +
 3 files changed, 30 insertions(+), 24 deletions(-)

diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c
index 07687b8..0e70f80 100644
--- a/src/mainboard/lenovo/x201/romstage.c
+++ b/src/mainboard/lenovo/x201/romstage.c
@@ -203,6 +203,18 @@ static inline u16 read_acpi16(u32 addr)
    return inw(DEFAULT_PMBASE | addr);
 }

+static void
+set_fsb_frequency(void)
+{
+	u8 block[5];
+	u16 fsbfreq = 62879;
+	smbus_block_read(0x69, 0, 5, block);
+	block[0] = fsbfreq;
+	block[1] = fsbfreq >> 8;
+
+	smbus_block_write(0x69, 0, 5, block);
+}
+
 void main(unsigned long bist)
 {
    u32 reg32;
@@ -287,6 +299,10 @@ void main(unsigned long bist)

timestamp_add_now(TS_BEFORE_INITRAM);

+	chipset_init(s3resume);
+
+	set_fsb_frequency();
+
    raminit(s3resume, spd_addrmap);

timestamp_add_now(TS_AFTER_INITRAM);
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index c5fe8ba..c967e39 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -3796,28 +3796,11 @@ static void dmi_setup(void)
 }
 #endif

-#if REAL
-static void
-set_fsb_frequency (void)
-{
-	u8 block[5];
-	u16 fsbfreq = 62879;
-	smbus_block_read(0x69, 0, 5, block);
-	block[0] = fsbfreq;
-	block[1] = fsbfreq >> 8;
-
-	smbus_block_write(0x69, 0, 5, block);
-}
-#endif
-
-void raminit(const int s3resume, const u8 *spd_addrmap)
+void chipset_init(const int s3resume)
 {
-	unsigned channel, slot, lane, rank;
-	int i;
-	struct raminfo info;
    u8 x2ca8;

-	gav(x2ca8 = read_mchbar8(0x2ca8));
+	x2ca8 = read_mchbar8(0x2ca8);
    if ((x2ca8 & 1) || (x2ca8 == 8 && !s3resume)) {
    	printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
    	write_mchbar8(0x2ca8, 0);
@@ -3879,12 +3862,18 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
    pcie_write_config16(NORTHBRIDGE, D0F0_GGC, 0xb50);
    gav(read32(DEFAULT_RCBA | 0x3428));
    write32(DEFAULT_RCBA | 0x3428, 0x1d);
+}

-#if !REAL
-	pre_raminit_5(s3resume);
-#else
-	set_fsb_frequency();
-#endif
+void raminit(const int s3resume, const u8 *spd_addrmap)
+{
+	unsigned channel, slot, lane, rank;
+	int i;
+	struct raminfo info;
+	u8 x2ca8;
+	u16 deven;
+
+	x2ca8 = read_mchbar8(0x2ca8);
+	deven = pcie_read_config16(NORTHBRIDGE, D0F0_DEVEN);

memset(&info, 0x5a, sizeof(info));

diff --git a/src/northbridge/intel/nehalem/raminit.h b/src/northbridge/intel/nehalem/raminit.h
index 91f0dea..0485694 100644
--- a/src/northbridge/intel/nehalem/raminit.h
+++ b/src/northbridge/intel/nehalem/raminit.h
@@ -22,6 +22,7 @@

#include "nehalem.h"

+void chipset_init(const int s3resume);
 /* spd_addrmap is array of 4 elements:
    Channel 0 Slot 0
    Channel 0 Slot 1