25 Apr
2020
25 Apr
'20
12:24 a.m.
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40588 )
Change subject: soc/intel/tigerlake: Fix FSP SPD index for DDR4 ......................................................................
Patch Set 2:
Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/2648 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2647 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2646 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/2645
Please note: This test is under development and might not be accurate at all!
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I2b6ea2433453a574970c1c33ff629fd54ff5d508
Gerrit-Change-Number: 40588
Gerrit-PatchSet: 2
Gerrit-Owner: Furquan Shaikh furquan@google.com
Gerrit-Reviewer: EricR Lai ericr_lai@compal.corp-partner.google.com
Gerrit-Reviewer: Furquan Shaikh furquan@google.com
Gerrit-Reviewer: Kane Chen kane.chen@intel.com
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
Gerrit-Reviewer: Tim Wawrzynczak twawrzynczak@chromium.org
Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org
Gerrit-CC: 9elements QA hardwaretestrobot@gmail.com
Gerrit-Comment-Date: Sat, 25 Apr 2020 06:24:25 +0000
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