Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47988 )
Change subject: soc/intel/common/dmi: Add DMI driver support ......................................................................
Patch Set 9:
(3 comments)
https://review.coreboot.org/c/coreboot/+/47988/9/src/soc/intel/common/block/... File src/soc/intel/common/block/dmi/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/47988/9/src/soc/intel/common/block/... PS9, Line 1: ifeq ($(CONFIG_SOC_INTEL_COMMON_BLOCK_DMI), y)
not necessary, all of the stages are already guarded with this, though you could also leave this one […]
Yeah that is a good point. I will fix this.
https://review.coreboot.org/c/coreboot/+/47988/9/src/soc/intel/common/block/... PS9, Line 6: smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_DMI) += dmi.c
is this used in SMM?
No. It was added here so that the linker can decide to optimize it out. I can drop smm and verstage since I don't think we would ever need it there (**famous last words**).
https://review.coreboot.org/c/coreboot/+/47988/9/src/soc/intel/common/block/... File src/soc/intel/common/block/dmi/dmi.c:
https://review.coreboot.org/c/coreboot/+/47988/9/src/soc/intel/common/block/... PS9, Line 8: #define MAX_GPMR_REGS 3 : : #define GPMR_OFFSET(x) (0x277c + (x) * 8) : #define DMI_PCR_GPMR_LIMIT_MASK 0xffff0000 : #define DMI_PCR_GPMR_BASE_SHIFT 16 : #define DMI_PCR_GPMR_BASE_MASK 0xffff : : #define GPMR_DID_OFFSET(x) (0x2780 + (x) * 8) : #define DMI_PCR_GPMR_EN BIT(31)
Do you mind lining up the right-hand side of these?
Srinidhi is OOO. I can fix this.