Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34541 )
Change subject: soc/intel/cannonlake: Allow coreboot to handle required chipset lockdown ......................................................................
Patch Set 2:
(4 comments)
https://review.coreboot.org/c/coreboot/+/34541/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34541/2//COMMIT_MSG@9 PS2, Line 9: let lets
https://review.coreboot.org/c/coreboot/+/34541/2//COMMIT_MSG@10 PS2, Line 10: chipset lockdown in ramstage. Why does coreboot need the chipset to be unlocked in ramstage?
https://review.coreboot.org/c/coreboot/+/34541/2//COMMIT_MSG@13 PS2, Line 13: suggested suggests
https://review.coreboot.org/c/coreboot/+/34541/2/src/soc/intel/cannonlake/fs... File src/soc/intel/cannonlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/34541/2/src/soc/intel/cannonlake/fs... PS2, Line 420: Spi SPI