Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42737 )
Change subject: soc/intel/cannonlake: Add UWES ASL into xhci.asl ......................................................................
soc/intel/cannonlake: Add UWES ASL into xhci.asl
Align support for enable wake-on-usb attach/detach as was introduced in Skylake in `commit 3bfe3404df32ca226c624be0435c640bf1ebeae7`.
This adds the USB Wake Enable Setup (UWES) ASL blocks required to inform the OS about plug wake events bits being set in the PORTSCN register configured by devicetree.
BUG=b:159187889 BRANCH=none TEST=none
Change-Id: I6c63d226e5acadff04486c8a6764fb715a0ac051 Signed-off-by: Edward O'Callaghan quasisec@google.com --- M src/soc/intel/cannonlake/acpi/xhci.asl 1 file changed, 63 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/42737/1
diff --git a/src/soc/intel/cannonlake/acpi/xhci.asl b/src/soc/intel/cannonlake/acpi/xhci.asl index d5187e6..fabe1f1 100644 --- a/src/soc/intel/cannonlake/acpi/xhci.asl +++ b/src/soc/intel/cannonlake/acpi/xhci.asl @@ -2,6 +2,61 @@
#include <soc/gpe.h>
+/* + * USB Port Wake Enable (UPWE) on usb attach/detach + * Arg0 - Port Number + * Arg1 - Port 1 Status and control offset + * Arg2 - xHCI Memory-mapped address + */ +Method (UPWE, 3, Serialized) +{ + /* Local0 = Arg1 + ((Arg0 - 1) * 0x10) */ + Add (Arg1, Multiply (Subtract (Arg0, 1), 0x10), Local0) + + /* Map ((XMEM << 16) + Local0 in PSCR */ + OperationRegion (PSCR, SystemMemory, + Add (ShiftLeft (Arg2, 16), Local0), 0x10) + Field (PSCR, DWordAcc, NoLock, Preserve) + { + PSCT, 32, + } + Store(PSCT, Local0) + /* + * And port status/control reg with RO and RWS bits + * RO bits: 0, 2:3, 10:13, 24, 28:30 + * RWS bits: 5:9, 14:16, 25:27 + */ + And (Local0, ~0x80FE0012, Local0) + /* Set WCE and WDE bits */ + Or (Local0, 0x6000000, Local0) + Store(Local0, PSCT) +} + +/* + * USB Wake Enable Setup (UWES) + * Arg0 - Port enable bitmap + * Arg1 - Port 1 Status and control offset + * Arg2 - xHCI Memory-mapped address + */ +Method (UWES, 3, Serialized) +{ + Store (Arg0, Local0) + + While (One) { + FindSetRightBit (Local0, Local1) + If (LEqual (Local1, Zero)) { + Break + } + UPWE (Local1, Arg1, Arg2) + /* + * Clear the lowest set bit in Local0 since it was + * processed. + * Local0 = Local0 & (Local0 - 1) + */ + And (Local0, Subtract (Local0, 1), Local0) + } +} + /* XHCI Controller 0:14.0 */
Device (XHCI) @@ -10,6 +65,14 @@
Name (_PRW, Package () { GPE0_PME_B0, 3 })
+ Name (_DSW, 3) + { + Store (Arg0, PMEE) + UWES (And (\U2WE, 0x3FF), 0x480, XMEM) + UWES (And (\U3WE, 0x3F ), 0x540, XMEM) + + } + Name (_S3D, 3) /* D3 supported in S3 */ Name (_S0W, 3) /* D3 can wake device in S0 */ Name (_S3W, 3) /* D3 can wake system from S3 */