Xi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44702 )
Change subject: soc/mediatek/mt8192: Do memory pll init before calibration ......................................................................
Patch Set 41:
(3 comments)
https://review.coreboot.org/c/coreboot/+/44702/40/src/soc/mediatek/mt8192/dr... File src/soc/mediatek/mt8192/dramc_pi_main.c:
https://review.coreboot.org/c/coreboot/+/44702/40/src/soc/mediatek/mt8192/dr... PS40, Line 28: tmp = read32(&mtk_apmixed->mpll_con3); : write32(&mtk_apmixed->mpll_con3, tmp & 0xfffffffd);
Use clrsetbits32()
Ack
https://review.coreboot.org/c/coreboot/+/44702/40/src/soc/mediatek/mt8192/dr... PS40, Line 33: tmp = read32(&mtk_apmixed->mpll_con0); : write32(&mtk_apmixed->mpll_con0, tmp | 0x1);
Use clrsetbits32()
Ack
https://review.coreboot.org/c/coreboot/+/44702/40/src/soc/mediatek/mt8192/dr... PS40, Line 37: tmp = read32(&mtk_apmixed->pllon_con0); : write32(&mtk_apmixed->pllon_con0, tmp & ~(0x1 << 2));
Use clrsetbits32(). Same below.
Ack