Timothy Pearson (tpearson@raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14241
-gerrit
commit f6292060631aeae0307cb713a4c2da4890d73e2b Author: Timothy Pearson tpearson@raptorengineeringinc.com Date: Mon Apr 4 14:24:23 2016 -0500
sb/amd/sp5100: Add ehci_async_data_cache CMOS option
SP5100 devices are affected by an erratum that can lock up the EHCI ports under certain conditions. Add an optional CMOS option to enable a workaround at the expense of performance.
Change-Id: I305d23dfa50f10a3dcb5c731e8923305c8956dde Signed-off-by: Timothy Pearson tpearson@raptorengineeringinc.com --- src/southbridge/amd/sb700/usb.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/src/southbridge/amd/sb700/usb.c b/src/southbridge/amd/sb700/usb.c index cd7378e..fe42c35 100644 --- a/src/southbridge/amd/sb700/usb.c +++ b/src/southbridge/amd/sb700/usb.c @@ -76,10 +76,16 @@ static void usb_init(struct device *dev)
static void usb_init2(struct device *dev) { - u32 dword; + uint32_t dword; void *usb2_bar0; device_t sm_dev; - u8 rev; + uint8_t rev; + uint8_t ehci_async_data_cache; + uint8_t nvram; + + ehci_async_data_cache = 1; + if (get_option(&nvram, "ehci_async_data_cache") == CB_SUCCESS) + ehci_async_data_cache = !!nvram;
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); rev = get_sb700_revision(sm_dev); @@ -174,6 +180,12 @@ static void usb_init2(struct device *dev) dword |= 1 << 8; dword &= ~(1 << 27); /* 6.23 */ } +#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100 + /* SP5100 Erratum 36 */ + dword &= ~(1 << 26); + if (!ehci_async_data_cache) + dword |= 1 << 26; +#endif pci_write_config32(dev, 0x50, dword); printk(BIOS_DEBUG, "rpr 6.23, final dword=%x\n", dword); }