[coreboot-gerrit] Change in coreboot[master]: drivers/genesyslogic/gl9755: Adjust L1 exit latency to enable ASPM

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47682 )

Change subject: drivers/genesyslogic/gl9755: Adjust L1 exit latency to enable ASPM
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Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/47682/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/47682/2//COMMIT_MSG@9 
PS2, Line 9: set the latency to <64us
Where is that limit documented, that means, where does it come from?