[coreboot-gerrit] [M] Change in coreboot[main]: [WIP]sb/intel/bd82x6x/acpi: Add GPIO code

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78436?usp=email )

Change subject: [WIP]sb/intel/bd82x6x/acpi: Add GPIO code
......................................................................

[WIP]sb/intel/bd82x6x/acpi: Add GPIO code

Implement SoC specific GPIO helper functions for acpigen:
- STXS
- CTXS
- GRXS
- GTXS

Add acpigen helper functions used by platform independent code.

Those functions aren't used yet, but are required to be present
to link the generic ACPI drivers.

Change-Id: I19780cfa26b217c87a04257dfd3be4b3d0544c41
Signed-off-by: Patrick Rudolph 
---
M src/southbridge/intel/bd82x6x/Makefile.inc
M src/southbridge/intel/bd82x6x/acpi/pch.asl
A src/southbridge/intel/bd82x6x/gpio.c
3 files changed, 154 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/78436/1

diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc
index 0a4cc83..5ca3471 100644
--- a/src/southbridge/intel/bd82x6x/Makefile.inc
+++ b/src/southbridge/intel/bd82x6x/Makefile.inc
@@ -19,6 +19,7 @@
 ramstage-y += me_common.c
 ramstage-y += smbus.c
 ramstage-y += ../common/pciehp.c
+ramstage-$(CONFIG_HAVE_ACPI_TABLES) += gpio.c

ramstage-y += me_status.c

diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl
index 157c8dc..bdce424 100644
--- a/src/southbridge/intel/bd82x6x/acpi/pch.asl
+++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl
@@ -50,6 +50,119 @@
    	GPEC, 1,	// SWGPE_CTRL
    }

+	OperationRegion (GPLV, SystemIO, DEFAULT_GPIOBASE, 0x6c)
+	Field (GPLV, AnyAcc, NoLock, Preserve)
+	{
+		Offset(0x0c),	// GPIO Level
+		LVL0, 32,
+		Offset(0x38),	// GPIO Level2
+		LVL1, 32,
+		Offset(0x48),	// GPIO Level3
+		LVL2, 12,
+	}
+
+	/*
+	 * Get GPIO level
+	 * Arg0 - GPIO Number
+	 * Returns: Level
+	 */
+	Method (GLVL, 0x1)
+	{
+		Local0 = Arg0 >> 5
+		If (Local0 == 0)
+		{
+			Local1 = LVL0
+		}
+		If (Local0 == 1)
+		{
+			Local1 = LVL1
+		}
+		If (Local0 == 2)
+		{
+			Local1 = LVL2
+		}
+		Local0 = Local1 >> (Arg0 & 0x1f)
+		Return (Local0 & 1)
+	}
+
+	/*
+	 * Set GPIO level
+	 * Arg0 - GPIO Number
+	 * Arg0 - Level
+	 */
+	Method (SLVL, 0x1)
+	{
+		Local0 = Arg0 >> 5
+		If (Local0 == 0)
+		{
+			Local1 = LVL0
+		}
+		If (Local0 == 1)
+		{
+			Local1 = LVL1
+		}
+		If (Local0 == 2)
+		{
+			Local1 = LVL2
+		}
+		If (Arg1 == 0)
+		{
+			Local1 &= ~(1 << (Arg0 & 0x1f))
+		}
+		Else
+		{
+			Local1 |= 1 << (Arg0 & 0x1f)
+		}
+		If (Local0 == 0)
+		{
+			LVL0 = Local1
+		}
+		If (Local0 == 1)
+		{
+			LVL1 = Local1
+		}
+		If (Local0 == 2)
+		{
+			LVL2 = Local1
+		}
+	}
+
+	/*
+	 * Set GPIO Output Value
+	 * Arg0 - GPIO Number
+	 */
+	Method (STXS, 1, Serialized)
+	{
+		SLVL(Arg0, 1)
+	}
+
+	/*
+	 * Clear GPIO Output Value
+	 * Arg0 - GPIO Number
+	 */
+	Method (CTXS, 1, Serialized)
+	{
+		SLVL(Arg0, 0)
+	}
+
+	/*
+	 * Get GPIO Input Value
+	 * Arg0 - GPIO Number
+	 */
+	Method (GRXS, 1, Serialized)
+	{
+		Return (GLVL(Arg0))
+	}
+
+	/*
+	 * Get GPIO Output Value
+	 * Arg0 - GPIO Number
+	 */
+	Method (GTXS, 1, Serialized)
+	{
+		Return (GLVL(Arg0))
+	}
+
    // GPIO IO mapped registers (0x1f.0 reg 0x48.l)
    OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x6c)
    Field(GPIO, ByteAcc, NoLock, Preserve)
diff --git a/src/southbridge/intel/bd82x6x/gpio.c b/src/southbridge/intel/bd82x6x/gpio.c
new file mode 100644
index 0000000..3e95433
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/gpio.c
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpigen.h>
+
+static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num)
+{
+	/* op (gpio_num) */
+	acpigen_emit_namestring(op);
+	acpigen_write_integer(gpio_num);
+	return 0;
+}
+
+static int acpigen_soc_get_gpio_state(const char *op, unsigned int gpio_num)
+{
+	/* Store (op (gpio_num), Local0) */
+	acpigen_write_store();
+	acpigen_soc_gpio_op(op, gpio_num);
+	acpigen_emit_byte(LOCAL0_OP);
+	return 0;
+}
+
+int acpigen_soc_read_rx_gpio(unsigned int gpio_num)
+{
+	return acpigen_soc_get_gpio_state("\_SB.GRXS", gpio_num);
+}
+
+int acpigen_soc_get_tx_gpio(unsigned int gpio_num)
+{
+	return acpigen_soc_get_gpio_state("\_SB.GTXS", gpio_num);
+}
+
+int acpigen_soc_set_tx_gpio(unsigned int gpio_num)
+{
+	return acpigen_soc_gpio_op("\_SB.STXS", gpio_num);
+}
+
+int acpigen_soc_clear_tx_gpio(unsigned int gpio_num)
+{
+	return acpigen_soc_gpio_op("\_SB.CTXS", gpio_num);
+}