Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37721 )
Change subject: soc/amd/common: Correct SPI FIFO size check ......................................................................
Patch Set 1:
Patch Set 1:
The implementation in soc/amd was probably forked while some other changes in SPI subsystem were in progress. Some things were probably lost in rebase, grep for SPI_CNTRLR_DEDUCT_CMD_LEN, notice it being used for {agesa,pi}/hudson.
Ideally amd/block/spi would work with hudson too.
We would've forked mid-2017. IIRC correctly from earlier this year, Richard was asked to write a brand new driver for common/block/spi and get us away from the generic one and variable length arrays. FWIW, it looks like we used to have SPI_CNTRLR_DEDUCT_CMD_LEN | _DEDUCT_OPCODE_LEN in our old spi.c. Things look a bit different now than hudson. I agree the common code should work on all AMD FCHs, but I never had the time to review his code closely. Not sure I see where VLAs went away yet.
I have pending work on it and will push a patch soon. AFAIK not all hudsons will be able to use the common SPI block (lack of shadow registers at SPIx4X)