Stefan Reinauer (stefan.reinauer@coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8110
-gerrit
commit b931f2c685d3fb2baa1e8919972fc2fdd27e4ee5 Author: Stefan Reinauer reinauer@chromium.org Date: Mon Jan 5 13:01:01 2015 -0800
southbridge: Drop print_ implementation from non-romcc boards
Because we have no stack on romcc boards, we had a separate, not as powerful clone of printk: print_*. Back in the day, like more than half a decade ago, we migrated a lot of boards to printk, but we never cleaned up the existing code to be consistent. instead, we worked around the problem with a very messy console.h (nowadays the mess is hidden in romstage_console.c and early_print.h) This patch cleans up the southbridge code to use printk() on all non-ROMCC boards.
Change-Id: I312406257e66bbdc3940e206b5256460559a2c98 Signed-off-by: Stefan Reinauer stefan.reinauer@coreboot.org --- src/southbridge/amd/amd8111/early_smbus.c | 2 +- src/southbridge/amd/cs5535/early_setup.c | 12 +++++------ src/southbridge/amd/cs5536/early_setup.c | 12 +++++------ src/southbridge/amd/cs5536/smbus.c | 6 +----- src/southbridge/broadcom/bcm5785/early_smbus.c | 2 +- src/southbridge/intel/bd82x6x/early_smbus.c | 2 +- src/southbridge/intel/esb6300/early_smbus.c | 4 ++-- src/southbridge/intel/fsp_bd82x6x/early_smbus.c | 2 +- src/southbridge/intel/fsp_rangeley/early_smbus.c | 2 +- src/southbridge/intel/i3100/early_smbus.c | 2 +- src/southbridge/intel/i82371eb/smbus.h | 4 +--- src/southbridge/intel/i82801ax/early_smbus.c | 2 +- src/southbridge/intel/i82801bx/early_smbus.c | 2 +- src/southbridge/intel/i82801cx/early_smbus.c | 2 +- src/southbridge/intel/i82801dx/early_smbus.c | 14 ++++++------- src/southbridge/intel/i82801ex/early_smbus.c | 8 ++++---- src/southbridge/intel/i82801gx/early_smbus.c | 2 +- src/southbridge/intel/i82801ix/early_smbus.c | 2 +- src/southbridge/intel/ibexpeak/early_smbus.c | 2 +- src/southbridge/intel/lynxpoint/early_smbus.c | 2 +- src/southbridge/intel/sch/early_smbus.c | 2 +- src/southbridge/nvidia/ck804/early_smbus.c | 2 +- src/southbridge/nvidia/mcp55/early_setup_car.c | 4 +--- src/southbridge/sis/sis966/aza.c | 17 +++++++--------- src/southbridge/sis/sis966/early_smbus.c | 22 ++++++++++---------- src/southbridge/sis/sis966/ide.c | 20 ++++++++---------- src/southbridge/sis/sis966/nic.c | 20 ++++++++---------- src/southbridge/sis/sis966/sata.c | 20 ++++++++---------- src/southbridge/sis/sis966/usb.c | 20 ++++++++---------- src/southbridge/sis/sis966/usb2.c | 20 ++++++++---------- src/southbridge/via/k8t890/bridge.c | 2 +- src/southbridge/via/k8t890/ctrl.c | 8 ++++---- src/southbridge/via/k8t890/dram.c | 2 +- src/southbridge/via/k8t890/early_car.c | 25 ++++++++++------------- src/southbridge/via/k8t890/error.c | 6 +++--- src/southbridge/via/k8t890/host.c | 2 +- src/southbridge/via/k8t890/host_ctrl.c | 2 +- src/southbridge/via/vt8237r/ctrl.c | 4 ++-- src/southbridge/via/vt8237r/early_smbus.c | 26 ++++++++++++------------ src/southbridge/via/vt8237r/vt8237r.c | 10 +++------ src/southbridge/via/vt8237r/vt8237r.h | 4 ++-- 41 files changed, 143 insertions(+), 181 deletions(-)
diff --git a/src/southbridge/amd/amd8111/early_smbus.c b/src/southbridge/amd/amd8111/early_smbus.c index e236286..aed4ebb 100644 --- a/src/southbridge/amd/amd8111/early_smbus.c +++ b/src/southbridge/amd/amd8111/early_smbus.c @@ -23,7 +23,7 @@ static void enable_smbus(void)
/* clear any lingering errors, so the transaction will run */ outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS); - print_spew("SMBus controller enabled\n"); + printk(BIOS_SPEW, "SMBus controller enabled\n"); }
static inline int smbus_recv_byte(unsigned device) diff --git a/src/southbridge/amd/cs5535/early_setup.c b/src/southbridge/amd/cs5535/early_setup.c index 4a2e1b4..1030aa0 100644 --- a/src/southbridge/amd/cs5535/early_setup.c +++ b/src/southbridge/amd/cs5535/early_setup.c @@ -127,19 +127,19 @@ static void cs5535_early_setup(void) msr = rdmsr(GLCP_SYS_RSTPLL); if (msr.lo & (0x3f << 26)) { /* PLL is already set and we are reboot from PLL reset */ - print_debug("reboot from BIOS reset\n"); + printk(BIOS_DEBUG, "reboot from BIOS reset\n"); return; } - print_debug("Setup idsel\n"); + printk(BIOS_DEBUG, "Setup idsel\n"); cs5535_setup_idsel(); - print_debug("Setup iobase\n"); + printk(BIOS_DEBUG, "Setup iobase\n"); cs5535_usb_swapsif(); cs5535_setup_iobase(); - print_debug("Setup gpio\n"); + printk(BIOS_DEBUG, "Setup gpio\n"); cs5535_setup_gpio(); - print_debug("Setup cis_mode\n"); + printk(BIOS_DEBUG, "Setup cis_mode\n"); cs5535_setup_cis_mode(); - print_debug("Setup smbus\n"); + printk(BIOS_DEBUG, "Setup smbus\n"); cs5535_enable_smbus(); dummy(); } diff --git a/src/southbridge/amd/cs5536/early_setup.c b/src/southbridge/amd/cs5536/early_setup.c index e6ef8ad..ea8b5e0 100644 --- a/src/southbridge/amd/cs5536/early_setup.c +++ b/src/southbridge/amd/cs5536/early_setup.c @@ -258,18 +258,18 @@ static void cs5536_early_setup(void) msr = rdmsr(GLCP_SYS_RSTPLL); if (msr.lo & (0x3f << 26)) { /* PLL is already set and we are reboot from PLL reset */ - //print_debug("reboot from BIOS reset\n"); + //printk(BIOS_DEBUG, "reboot from BIOS reset\n"); return; } - //print_debug("Setup idsel\n"); + //printk(BIOS_DEBUG, "Setup idsel\n"); cs5536_setup_idsel(); - //print_debug("Setup iobase\n"); + //printk(BIOS_DEBUG, "Setup iobase\n"); cs5536_usb_swapsif(); cs5536_setup_iobase(); - //print_debug("Setup gpio\n"); + //printk(BIOS_DEBUG, "Setup gpio\n"); cs5536_setup_gpio(); - //print_debug("Setup smbus\n"); + //printk(BIOS_DEBUG, "Setup smbus\n"); cs5536_enable_smbus(); - //print_debug("Setup power button\n"); + //printk(BIOS_DEBUG, "Setup power button\n"); cs5536_setup_power_button(); } diff --git a/src/southbridge/amd/cs5536/smbus.c b/src/southbridge/amd/cs5536/smbus.c index 31c5bf1..3da8389 100644 --- a/src/southbridge/amd/cs5536/smbus.c +++ b/src/southbridge/amd/cs5536/smbus.c @@ -182,11 +182,7 @@ unsigned char do_smbus_read_byte(unsigned smbus_io_base, return smbus_get_result(smbus_io_base);
err: - print_debug("SMBUS READ ERROR:"); - print_debug_hex8(error); - print_debug(" device:"); - print_debug_hex8(device); - print_debug("\n"); + printk(BIOS_DEBUG, "SMBUS READ ERROR: %02x device: %02x\n", error, device); /* stop, clean up the error, and leave */ smbus_stop_condition(smbus_io_base); outb(inb(smbus_io_base + SMB_STS), smbus_io_base + SMB_STS); diff --git a/src/southbridge/broadcom/bcm5785/early_smbus.c b/src/southbridge/broadcom/bcm5785/early_smbus.c index 38e58f8..636da2e 100644 --- a/src/southbridge/broadcom/bcm5785/early_smbus.c +++ b/src/southbridge/broadcom/bcm5785/early_smbus.c @@ -31,7 +31,7 @@ static void enable_smbus(void) die("SMBUS controller not found\n"); }
- print_debug("SMBus controller enabled\n"); + printk(BIOS_DEBUG, "SMBus controller enabled\n"); /* set smbus iobase */ pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1); /* Set smbus iospace enable */ diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c index 616e7c3..7ba2e88 100644 --- a/src/southbridge/intel/bd82x6x/early_smbus.c +++ b/src/southbridge/intel/bd82x6x/early_smbus.c @@ -52,7 +52,7 @@ void enable_smbus(void)
/* Clear any lingering errors, so transactions can run. */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - print_debug("SMBus controller enabled.\n"); + printk(BIOS_DEBUG, "SMBus controller enabled.\n"); }
int smbus_read_byte(unsigned device, unsigned address) diff --git a/src/southbridge/intel/esb6300/early_smbus.c b/src/southbridge/intel/esb6300/early_smbus.c index fbbf4d9..9ad4f65 100644 --- a/src/southbridge/intel/esb6300/early_smbus.c +++ b/src/southbridge/intel/esb6300/early_smbus.c @@ -6,7 +6,7 @@ static void enable_smbus(void) { device_t dev = PCI_DEV(0x0, 0x1f, 0x3);
- print_spew("SMBus controller enabled\n"); + printk(BIOS_SPEW, "SMBus controller enabled\n"); pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); pci_write_config8(dev, 0x40, 1); pci_write_config8(dev, 0x4, 1); @@ -91,7 +91,7 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd, SMBUS_IO_BASE + SMBHSTSTAT); }
- print_debug("SMBUS Block complete\n"); + printk(BIOS_DEBUG, "SMBUS Block complete\n"); return 0; } #endif diff --git a/src/southbridge/intel/fsp_bd82x6x/early_smbus.c b/src/southbridge/intel/fsp_bd82x6x/early_smbus.c index 3d347b4..c5459cb 100644 --- a/src/southbridge/intel/fsp_bd82x6x/early_smbus.c +++ b/src/southbridge/intel/fsp_bd82x6x/early_smbus.c @@ -97,7 +97,7 @@ void enable_smbus(void)
/* Clear any lingering errors, so transactions can run. */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - print_debug("SMBus controller enabled.\n"); + printk(BIOS_DEBUG, "SMBus controller enabled.\n"); }
/** \brief generic smbus helper function to read & write to the smbus diff --git a/src/southbridge/intel/fsp_rangeley/early_smbus.c b/src/southbridge/intel/fsp_rangeley/early_smbus.c index c89d176..c1da54b 100644 --- a/src/southbridge/intel/fsp_rangeley/early_smbus.c +++ b/src/southbridge/intel/fsp_rangeley/early_smbus.c @@ -52,7 +52,7 @@ void enable_smbus(void)
/* Clear any lingering errors, so transactions can run. */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - print_debug("SMBus controller enabled.\n"); + printk(BIOS_DEBUG, "SMBus controller enabled.\n"); }
int smbus_read_byte(unsigned device, unsigned address) diff --git a/src/southbridge/intel/i3100/early_smbus.c b/src/southbridge/intel/i3100/early_smbus.c index f06947c..484627c 100644 --- a/src/southbridge/intel/i3100/early_smbus.c +++ b/src/southbridge/intel/i3100/early_smbus.c @@ -26,7 +26,7 @@ static void enable_smbus(void) { device_t dev = PCI_DEV(0x0, 0x1f, 0x3);
- print_spew("SMBus controller enabled\n"); + printk(BIOS_SPEW, "SMBus controller enabled\n"); pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); pci_write_config8(dev, 0x40, 1); pci_write_config8(dev, 0x4, 1); diff --git a/src/southbridge/intel/i82371eb/smbus.h b/src/southbridge/intel/i82371eb/smbus.h index 6c7c6f4..fd02217 100644 --- a/src/southbridge/intel/i82371eb/smbus.h +++ b/src/southbridge/intel/i82371eb/smbus.h @@ -104,9 +104,7 @@ int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address
if (status_register & 0x04) { #if 0 - print_debug("Read fail "); - print_debug_hex16(status_register); - print_debug("\n"); + printk(BIOS_DEBUG, "Read fail %04x\n", status_register); #endif return SMBUS_ERROR; } diff --git a/src/southbridge/intel/i82801ax/early_smbus.c b/src/southbridge/intel/i82801ax/early_smbus.c index 878d5f6..104875a 100644 --- a/src/southbridge/intel/i82801ax/early_smbus.c +++ b/src/southbridge/intel/i82801ax/early_smbus.c @@ -50,7 +50,7 @@ void enable_smbus(void) /* Clear any lingering errors, so transactions can run. */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
- print_debug("SMBus controller enabled\n"); + printk(BIOS_DEBUG, "SMBus controller enabled\n"); }
int smbus_read_byte(u8 device, u8 address) diff --git a/src/southbridge/intel/i82801bx/early_smbus.c b/src/southbridge/intel/i82801bx/early_smbus.c index 26c9e85..a87a4a7 100644 --- a/src/southbridge/intel/i82801bx/early_smbus.c +++ b/src/southbridge/intel/i82801bx/early_smbus.c @@ -50,7 +50,7 @@ void enable_smbus(void) /* Clear any lingering errors, so transactions can run. */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
- print_debug("SMBus controller enabled\n"); + printk(BIOS_DEBUG, "SMBus controller enabled\n"); }
int smbus_read_byte(u8 device, u8 address) diff --git a/src/southbridge/intel/i82801cx/early_smbus.c b/src/southbridge/intel/i82801cx/early_smbus.c index b62db80..5be6353 100644 --- a/src/southbridge/intel/i82801cx/early_smbus.c +++ b/src/southbridge/intel/i82801cx/early_smbus.c @@ -5,7 +5,7 @@ static void enable_smbus(void) { device_t dev = PCI_DEV(0x0, 0x1f, 0x3);
- print_debug("SMBus controller enabled\n"); + printk(BIOS_DEBUG, "SMBus controller enabled\n"); /* set smbus iobase */ pci_write_config32(dev, SMB_BASE, SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); /* Set smbus enable */ diff --git a/src/southbridge/intel/i82801dx/early_smbus.c b/src/southbridge/intel/i82801dx/early_smbus.c index 6f4d4f8..c61de85 100644 --- a/src/southbridge/intel/i82801dx/early_smbus.c +++ b/src/southbridge/intel/i82801dx/early_smbus.c @@ -28,7 +28,7 @@ void enable_smbus(void) { device_t dev = PCI_DEV(0x0, 0x1f, 0x3);
- print_debug("SMBus controller enabled\n"); + printk(BIOS_DEBUG, "SMBus controller enabled\n"); /* set smbus iobase */ pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); /* Set smbus enable */ @@ -104,9 +104,9 @@ int smbus_read_byte(unsigned device, unsigned address) unsigned char global_status_register; unsigned char byte;
- /* print_err("smbus_read_byte\n"); */ + /* printk(BIOS_ERR, "smbus_read_byte\n"); */ if (smbus_wait_until_ready() < 0) { - print_err("SMBUS not ready (-2)\n"); + printk(BIOS_ERR, "SMBUS not ready (-2)\n"); return -2; }
@@ -132,13 +132,13 @@ int smbus_read_byte(unsigned device, unsigned address) SMBUS_IO_BASE + SMBHSTCTL); /* poll for it to start */ if (smbus_wait_until_active() < 0) { - print_err("SMBUS not active (-4)\n"); + printk(BIOS_ERR, "SMBUS not active (-4)\n"); return -4; }
/* poll for transaction completion */ if (smbus_wait_until_done() < 0) { - print_err("SMBUS not completed (-3)\n"); + printk(BIOS_ERR, "SMBUS not completed (-3)\n"); return -3; }
@@ -148,10 +148,10 @@ int smbus_read_byte(unsigned device, unsigned address) byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
if (global_status_register != 2) { - //print_spew("%s: no device (%02x, %02x)\n", __func__, device, address); + //printk(BIOS_SPEW, "%s: no device (%02x, %02x)\n", __func__, device, address); return -1; } - //print_debug("%s: %02x@%02x = %02x\n", __func__, device, address, byte); + //printk(BIOS_DEBUG, "%s: %02x@%02x = %02x\n", __func__, device, address, byte); return byte; }
diff --git a/src/southbridge/intel/i82801ex/early_smbus.c b/src/southbridge/intel/i82801ex/early_smbus.c index cdf1f62..979b842 100644 --- a/src/southbridge/intel/i82801ex/early_smbus.c +++ b/src/southbridge/intel/i82801ex/early_smbus.c @@ -6,10 +6,10 @@ static void enable_smbus(void) { device_t dev = PCI_DEV(0x0, 0x1f, 0x3);
- print_spew("SMBus controller enabled\n"); + printk(BIOS_SPEW, "SMBus controller enabled\n");
pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); - print_debug_hex32(pci_read_config32(dev, 0x20)); + printk(BIOS_DEBUG, "%08x", pci_read_config32(dev, 0x20)); /* Set smbus enable */ pci_write_config8(dev, 0x40, 1); /* Set smbus iospace enable */ @@ -36,7 +36,7 @@ static void smbus_write_byte(unsigned device, unsigned address, unsigned char va return; }
- print_debug("Unimplemented smbus_write_byte() called.\n"); + printk(BIOS_DEBUG, "Unimplemented smbus_write_byte() called.\n");
#if 0 /* setup transaction */ @@ -124,7 +124,7 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd, SMBUS_IO_BASE + SMBHSTSTAT); }
- print_debug("SMBUS Block complete\n"); + printk(BIOS_DEBUG, "SMBUS Block complete\n"); return 0; } #endif diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c index 8adc04d..32eccae 100644 --- a/src/southbridge/intel/i82801gx/early_smbus.c +++ b/src/southbridge/intel/i82801gx/early_smbus.c @@ -52,7 +52,7 @@ void enable_smbus(void)
/* Clear any lingering errors, so transactions can run. */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - print_debug("SMBus controller enabled.\n"); + printk(BIOS_DEBUG, "SMBus controller enabled.\n"); }
int smbus_read_byte(unsigned device, unsigned address) diff --git a/src/southbridge/intel/i82801ix/early_smbus.c b/src/southbridge/intel/i82801ix/early_smbus.c index 981ae5e..0393c3d 100644 --- a/src/southbridge/intel/i82801ix/early_smbus.c +++ b/src/southbridge/intel/i82801ix/early_smbus.c @@ -53,7 +53,7 @@ void enable_smbus(void)
/* Clear any lingering errors, so transactions can run. */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - print_debug("SMBus controller enabled.\n"); + printk(BIOS_DEBUG, "SMBus controller enabled.\n"); }
int smbus_read_byte(unsigned device, unsigned address) diff --git a/src/southbridge/intel/ibexpeak/early_smbus.c b/src/southbridge/intel/ibexpeak/early_smbus.c index f518f28..cf02b9e 100644 --- a/src/southbridge/intel/ibexpeak/early_smbus.c +++ b/src/southbridge/intel/ibexpeak/early_smbus.c @@ -52,7 +52,7 @@ void enable_smbus(void)
/* Clear any lingering errors, so transactions can run. */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - print_debug("SMBus controller enabled.\n"); + printk(BIOS_DEBUG, "SMBus controller enabled.\n"); }
int smbus_read_byte(unsigned device, unsigned address) diff --git a/src/southbridge/intel/lynxpoint/early_smbus.c b/src/southbridge/intel/lynxpoint/early_smbus.c index 616e7c3..7ba2e88 100644 --- a/src/southbridge/intel/lynxpoint/early_smbus.c +++ b/src/southbridge/intel/lynxpoint/early_smbus.c @@ -52,7 +52,7 @@ void enable_smbus(void)
/* Clear any lingering errors, so transactions can run. */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - print_debug("SMBus controller enabled.\n"); + printk(BIOS_DEBUG, "SMBus controller enabled.\n"); }
int smbus_read_byte(unsigned device, unsigned address) diff --git a/src/southbridge/intel/sch/early_smbus.c b/src/southbridge/intel/sch/early_smbus.c index 8adc04d..32eccae 100644 --- a/src/southbridge/intel/sch/early_smbus.c +++ b/src/southbridge/intel/sch/early_smbus.c @@ -52,7 +52,7 @@ void enable_smbus(void)
/* Clear any lingering errors, so transactions can run. */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - print_debug("SMBus controller enabled.\n"); + printk(BIOS_DEBUG, "SMBus controller enabled.\n"); }
int smbus_read_byte(unsigned device, unsigned address) diff --git a/src/southbridge/nvidia/ck804/early_smbus.c b/src/southbridge/nvidia/ck804/early_smbus.c index a8c12a2..e0f8648 100644 --- a/src/southbridge/nvidia/ck804/early_smbus.c +++ b/src/southbridge/nvidia/ck804/early_smbus.c @@ -54,7 +54,7 @@ void enable_smbus(void) outb(inb(SMBUS_BASE(0) + SMBHSTSTAT), SMBUS_BASE(0) + SMBHSTSTAT); outb(inb(SMBUS_BASE(1) + SMBHSTSTAT), SMBUS_BASE(1) + SMBHSTSTAT);
- print_debug("SMBus controller enabled\n"); + printk(BIOS_DEBUG, "SMBus controller enabled\n"); }
int ck804_smbus_read_byte(unsigned bus, unsigned device, unsigned address) diff --git a/src/southbridge/nvidia/mcp55/early_setup_car.c b/src/southbridge/nvidia/mcp55/early_setup_car.c index 4b1443c..2e03d6b 100644 --- a/src/southbridge/nvidia/mcp55/early_setup_car.c +++ b/src/southbridge/nvidia/mcp55/early_setup_car.c @@ -392,9 +392,7 @@ static int mcp55_early_setup_x(void) }
out: - print_debug("mcp55_num:"); - print_debug_hex8(mcp55_num); - print_debug("\n"); + printk(BIOS_DEBUG, "mcp55_num: %02x\n", mcp55_num);
mcp55_early_set_port(mcp55_num, busn, devn, io_base); mcp55_early_setup(mcp55_num, busn, devn, io_base, pci_e_x); diff --git a/src/southbridge/sis/sis966/aza.c b/src/southbridge/sis/sis966/aza.c index 7e148cf..1a9462b 100644 --- a/src/southbridge/sis/sis966/aza.c +++ b/src/southbridge/sis/sis966/aza.c @@ -244,7 +244,7 @@ static void aza_init(struct device *dev) struct resource *res; u32 codec_mask;
- print_debug("AZALIA_INIT:---------->\n"); + printk(BIOS_DEBUG, "AZALIA_INIT:---------->\n");
//-------------- enable AZA (SiS7502) ------------------------- { @@ -269,19 +269,16 @@ static void aza_init(struct device *dev) { int i;
- print_debug("****** Azalia PCI config ******"); - print_debug("\n 03020100 07060504 0B0A0908 0F0E0D0C"); + printk(BIOS_DEBUG, "****** Azalia PCI config ******"); + printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
for(i=0;i<0xff;i+=4){ if((i%16)==0){ - print_debug("\n"); - print_debug_hex8(i); - print_debug(": "); + printk(BIOS_DEBUG, "\n%02x: ", i); } - print_debug_hex32(pci_read_config32(dev,i)); - print_debug(" "); + printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); } - print_debug("\n"); + printk(BIOS_DEBUG, "\n"); } #endif
@@ -299,7 +296,7 @@ static void aza_init(struct device *dev) codecs_init(base, codec_mask); }
- print_debug("AZALIA_INIT:<----------\n"); + printk(BIOS_DEBUG, "AZALIA_INIT:<----------\n"); }
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) diff --git a/src/southbridge/sis/sis966/early_smbus.c b/src/southbridge/sis/sis966/early_smbus.c index 06130db..079e4b0 100644 --- a/src/southbridge/sis/sis966/early_smbus.c +++ b/src/southbridge/sis/sis966/early_smbus.c @@ -138,23 +138,23 @@ static inline int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, un outb(0x12, smbus_io_base + 0x03); smbus_delay();
-int i,j; -for(i=0;i<0x1000;i++) -{ - if (inb(smbus_io_base + 0x00) != 0x08) - { smbus_delay(); - for(j=0;j<0xFFFF;j++); + int i, j; + for(i = 0;i < 0x1000; i++) + { + if (inb(smbus_io_base + 0x00) != 0x08) + { smbus_delay(); + for(j=0;j<0xFFFF;j++); + } } -};
global_status_register = inb(smbus_io_base + 0x00); byte = inb(smbus_io_base + 0x08);
if (global_status_register != 0x08) { // lose check, otherwise it should be 0 - print_debug("Fail");print_debug("\r\t"); - return -1; + printk(BIOS_DEBUG, "Fail\r\t"); + return -1; } - print_debug("Success");print_debug("\r\t"); + printk(BIOS_DEBUG, "Success\r\t"); return byte; }
@@ -706,7 +706,7 @@ static void sis_init_stage2(void) dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_SATA), 0);
if (!dev) - print_debug("SiS 1183 does not exist !!"); + printk(BIOS_DEBUG, "SiS 1183 does not exist !!"); // SATA Set Mode pci_write_config8(dev, 0x90, (pci_read_config8(dev, 0x90)&0x3F) | 0x40);
diff --git a/src/southbridge/sis/sis966/ide.c b/src/southbridge/sis/sis966/ide.c index ddfcead..5300b7e 100644 --- a/src/southbridge/sis/sis966/ide.c +++ b/src/southbridge/sis/sis966/ide.c @@ -100,7 +100,7 @@ static void ide_init(struct device *dev)
-print_debug("IDE_INIT:---------->\n"); +printk(BIOS_DEBUG, "IDE_INIT:---------->\n");
//-------------- enable IDE (SiS5513) ------------------------- @@ -149,22 +149,18 @@ print_debug("IDE_INIT:---------->\n"); { int i;
- print_debug("****** IDE PCI config ******"); - print_debug("\n 03020100 07060504 0B0A0908 0F0E0D0C"); + printk(BIOS_DEBUG, "****** IDE PCI config ******"); + printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
for(i=0;i<0xff;i+=4){ - if((i%16)==0){ - print_debug("\n"); - print_debug_hex8(i); - print_debug(": "); - } - print_debug_hex32(pci_read_config32(dev,i)); - print_debug(" "); + if((i%16)==0) + printk(BIOS_DEBUG, "\n%02x: ", i); + printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); } - print_debug("\n"); + printk(BIOS_DEBUG, "\n"); } #endif -print_debug("IDE_INIT:<----------\n"); +printk(BIOS_DEBUG, "IDE_INIT:<----------\n"); }
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) diff --git a/src/southbridge/sis/sis966/nic.c b/src/southbridge/sis/sis966/nic.c index 18ed75e..b12c831 100644 --- a/src/southbridge/sis/sis966/nic.c +++ b/src/southbridge/sis/sis966/nic.c @@ -241,7 +241,7 @@ static void nic_init(struct device *dev) u32 base; struct resource *res;
- print_debug("NIC_INIT:---------->\n"); + printk(BIOS_DEBUG, "NIC_INIT:---------->\n");
//-------------- enable NIC (SiS19x) ------------------------- { @@ -312,19 +312,15 @@ static void nic_init(struct device *dev) { int i;
- print_debug("****** NIC PCI config ******"); - print_debug("\n 03020100 07060504 0B0A0908 0F0E0D0C"); + printk(BIOS_DEBUG, "****** NIC PCI config ******"); + printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
for(i=0;i<0xff;i+=4){ - if((i%16)==0){ - print_debug("\n"); - print_debug_hex8(i); - print_debug(": "); - } - print_debug_hex32(pci_read_config32(dev,i)); - print_debug(" "); + if((i%16)==0) + printk(BIOS_DEBUG, "\n%02x: ", i); + printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); } - print_debug("\n"); + printk(BIOS_DEBUG, "\n"); }
@@ -332,7 +328,7 @@ static void nic_init(struct device *dev)
}
-print_debug("NIC_INIT:<----------\n"); +printk(BIOS_DEBUG, "NIC_INIT:<----------\n"); return;
diff --git a/src/southbridge/sis/sis966/sata.c b/src/southbridge/sis/sis966/sata.c index 3f8c28f..ade8c1c 100644 --- a/src/southbridge/sis/sis966/sata.c +++ b/src/southbridge/sis/sis966/sata.c @@ -116,7 +116,7 @@ static void sata_init(struct device *dev)
conf = dev->chip_info; - print_debug("SATA_INIT:---------->\n"); + printk(BIOS_DEBUG, "SATA_INIT:---------->\n");
//-------------- enable IDE (SiS1183) ------------------------- { @@ -151,23 +151,19 @@ for (i=0;i<10;i++){ { int i;
- print_debug("****** SATA PCI config ******"); - print_debug("\n 03020100 07060504 0B0A0908 0F0E0D0C"); + printk(BIOS_DEBUG, "****** SATA PCI config ******"); + printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
for(i=0;i<0xff;i+=4){ - if((i%16)==0){ - print_debug("\n"); - print_debug_hex8(i); - print_debug(": "); - } - print_debug_hex32(pci_read_config32(dev,i)); - print_debug(" "); + if((i%16)==0) + printk(BIOS_DEBUG, "\n%02x: ", i); + printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); } - print_debug("\n"); + printk(BIOS_DEBUG, "\n"); } #endif
- print_debug("SATA_INIT:<----------\n"); + printk(BIOS_DEBUG, "SATA_INIT:<----------\n");
}
diff --git a/src/southbridge/sis/sis966/usb.c b/src/southbridge/sis/sis966/usb.c index c33f0fc..5aedefb 100644 --- a/src/southbridge/sis/sis966/usb.c +++ b/src/southbridge/sis/sis966/usb.c @@ -55,7 +55,7 @@ uint8_t SiS_SiS7001_init[16][3]={
static void usb_init(struct device *dev) { - print_debug("USB 1.1 INIT:---------->\n"); + printk(BIOS_DEBUG, "USB 1.1 INIT:---------->\n");
//-------------- enable USB1.1 (SiS7001) ------------------------- { @@ -76,22 +76,18 @@ static void usb_init(struct device *dev) { int i;
- print_debug("****** USB 1.1 PCI config ******"); - print_debug("\n 03020100 07060504 0B0A0908 0F0E0D0C"); + printk(BIOS_DEBUG, "****** USB 1.1 PCI config ******"); + printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
for(i=0;i<0xff;i+=4){ - if((i%16)==0){ - print_debug("\n"); - print_debug_hex8(i); - print_debug(": "); - } - print_debug_hex32(pci_read_config32(dev,i)); - print_debug(" "); + if((i%16)==0) + printk(BIOS_DEBUG, "\n%02x: ", i); + printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); } - print_debug("\n"); + printk(BIOS_DEBUG, "\n"); } #endif - print_debug("USB 1.1 INIT:<----------\n"); + printk(BIOS_DEBUG, "USB 1.1 INIT:<----------\n"); }
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) diff --git a/src/southbridge/sis/sis966/usb2.c b/src/southbridge/sis/sis966/usb2.c index e2112eb..c6f4027 100644 --- a/src/southbridge/sis/sis966/usb2.c +++ b/src/southbridge/sis/sis966/usb2.c @@ -71,7 +71,7 @@ static void usb2_init(struct device *dev) int i; u8 temp8;
- print_debug("USB 2.0 INIT:---------->\n"); + printk(BIOS_DEBUG, "USB 2.0 INIT:---------->\n");
//-------------- enable USB2.0 (SiS7002) ----------------------
@@ -95,21 +95,17 @@ static void usb2_init(struct device *dev) //-------------------------------------------------------------
#if DEBUG_USB2 - print_debug("****** USB 2.0 PCI config ******"); - print_debug("\n 03020100 07060504 0B0A0908 0F0E0D0C"); + printk(BIOS_DEBUG, "****** USB 2.0 PCI config ******"); + printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
for(i=0;i<0xff;i+=4){ - if((i%16)==0){ - print_debug("\n"); - print_debug_hex8(i); - print_debug(": "); - } - print_debug_hex32(pci_read_config32(dev,i)); - print_debug(" "); + if((i%16)==0) + printk(BIOS_DEBUG, "\n%02x: ", i); + printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); } - print_debug("\n"); + printk(BIOS_DEBUG, "\n"); #endif - print_debug("USB 2.0 INIT:<----------\n"); + printk(BIOS_DEBUG, "USB 2.0 INIT:<----------\n"); }
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) diff --git a/src/southbridge/via/k8t890/bridge.c b/src/southbridge/via/k8t890/bridge.c index 2da31f4..fdf5b9d 100644 --- a/src/southbridge/via/k8t890/bridge.c +++ b/src/southbridge/via/k8t890/bridge.c @@ -26,7 +26,7 @@ static void bridge_enable(struct device *dev) { u8 tmp; - print_debug("B188 device dump\n"); + printk(BIOS_DEBUG, "B188 device dump\n");
/* VIA recommends this, sorry no known info. */
diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c index a918f01..782c547 100644 --- a/src/southbridge/via/k8t890/ctrl.c +++ b/src/southbridge/via/k8t890/ctrl.c @@ -152,7 +152,7 @@ static void vt8237r_vlink_init(struct device *dev) static void ctrl_init(struct device *dev) {
- print_debug("K8x8xx: Initializing V-Link to VT8237R sb: "); + printk(BIOS_DEBUG, "K8x8xx: Initializing V-Link to VT8237R sb: "); /* TODO: Fix some ordering issue for V-link set Rx77[6] and PCI1_Rx4F[0] should to 1 */
@@ -172,11 +172,11 @@ static void ctrl_init(struct device *dev) vt8237r_vlink_init(dev); k8x8xx_vt8237r_cfg(dev, devsb); } else { - print_debug("VT8237R LPC not found !\n"); + printk(BIOS_DEBUG, "VT8237R LPC not found !\n"); return; } - print_debug(" Done\n"); - print_debug(" VIA_X_7 device dump:\n"); + printk(BIOS_DEBUG, " Done\n"); + printk(BIOS_DEBUG, " VIA_X_7 device dump:\n"); dump_south(dev);
} diff --git a/src/southbridge/via/k8t890/dram.c b/src/southbridge/via/k8t890/dram.c index 07a34b7..04184b7 100644 --- a/src/southbridge/via/k8t890/dram.c +++ b/src/southbridge/via/k8t890/dram.c @@ -66,7 +66,7 @@ static void dram_enable(struct device *dev) /* The Address Next to the Last Valid DRAM Address */ pci_write_config16(dev, 0x88, reg | mregs.shadow_mem_ctrl);
- print_debug(" VIA_X_3 device dump:\n"); + printk(BIOS_DEBUG, " VIA_X_3 device dump:\n"); dump_south(dev);
} diff --git a/src/southbridge/via/k8t890/early_car.c b/src/southbridge/via/k8t890/early_car.c index d7049ae..7eba967 100644 --- a/src/southbridge/via/k8t890/early_car.c +++ b/src/southbridge/via/k8t890/early_car.c @@ -80,23 +80,23 @@ u8 k8t890_early_setup_ht(void) }
#if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M800 - print_debug("K8M800 found at LDT "); + printk(BIOS_DEBUG, "K8M800 found at LDT "); #elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800 - print_debug("K8T800 found at LDT "); + printk(BIOS_DEBUG, "K8T800 found at LDT "); #elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD - print_debug("K8T800_OLD found at LDT "); + printk(BIOS_DEBUG, "K8T800_OLD found at LDT "); pci_write_config8(PCI_DEV(0, 0x0, 0), 0x64, 0x00); pci_write_config8(PCI_DEV(0, 0x0, 0), 0xdd, 0x50); #elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800PRO - print_debug("K8T800 Pro found at LDT "); + printk(BIOS_DEBUG, "K8T800 Pro found at LDT "); #elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M890 - print_debug("K8M890 found at LDT "); + printk(BIOS_DEBUG, "K8M890 found at LDT "); /* K8M890 fix HT delay */ pci_write_config8(PCI_DEV(0, 0x0, 2), 0xab, 0x22); #elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T890 - print_debug("K8T890 found at LDT "); + printk(BIOS_DEBUG, "K8T890 found at LDT "); #endif - print_debug_hex8(ldtnr); + printk(BIOS_DEBUG, "%02x", ldtnr);
/* get the maximum widths for both sides */ cldtwidth_in = pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr]) & 0x7; @@ -105,8 +105,7 @@ u8 k8t890_early_setup_ht(void) vldtwidth_out = (pci_read_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0x6) >> 4) & 0x7;
width = MIN(MIN(MIN(cldtwidth_out, cldtwidth_in), vldtwidth_out), vldtwidth_in); - print_debug(" Agreed on width: "); - print_debug_hex8(width); + printk(BIOS_DEBUG, " Agreed on width: %02x", width);
awidth = pci_read_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0x7);
@@ -117,12 +116,10 @@ u8 k8t890_early_setup_ht(void)
/* Get programmed HT freq at base 0x89 */ cldtfreq = pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr] + 3) & 0xf; - print_debug(" CPU programmed to HT freq: "); - print_debug_hex8(cldtfreq); + printk(BIOS_DEBUG, " CPU programmed to HT freq: %02x", cldtfreq);
- print_debug(" VIA HT caps: "); vldtcaps = pci_read_config16(PCI_DEV(0, 0, 0), K8X8XX_HT_CFG_BASE + 0xe); - print_debug_hex16(vldtcaps); + printk(BIOS_DEBUG, " VIA HT caps: %04x", vldtcaps);
if (!(vldtcaps & (1 << cldtfreq ))) { die("Chipset does not support desired HT frequency\n"); @@ -130,7 +127,7 @@ u8 k8t890_early_setup_ht(void)
afreq = pci_read_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0xd); pci_write_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0xd, cldtfreq); - print_debug("\n"); + printk(BIOS_DEBUG, "\n");
/* no reset needed */ if ((width == awidth) && (afreq == cldtfreq)) { diff --git a/src/southbridge/via/k8t890/error.c b/src/southbridge/via/k8t890/error.c index 0870288..2c1b5b6 100644 --- a/src/southbridge/via/k8t890/error.c +++ b/src/southbridge/via/k8t890/error.c @@ -26,7 +26,7 @@
static void error_enable(struct device *dev) { - print_debug(" K8x8xx: Enabling NB error reporting: "); + printk(BIOS_DEBUG, " K8x8xx: Enabling NB error reporting: "); /* * bit0 - Enable V-link parity error reporting in 0x50 bit0 (RWC) * bit6 - Parity Error/SERR# Report Through V-Link to SB @@ -34,10 +34,10 @@ static void error_enable(struct device *dev) */ pci_write_config8(dev, 0x58, 0x81);
- print_debug("Done\n"); + printk(BIOS_DEBUG, "Done\n"); /* TODO: enable AGP errors reporting on K8M890 */
- print_debug(" VIA_X_1 device dump:\n"); + printk(BIOS_DEBUG, " VIA_X_1 device dump:\n"); dump_south(dev); }
diff --git a/src/southbridge/via/k8t890/host.c b/src/southbridge/via/k8t890/host.c index aa1b748..878ee9a 100644 --- a/src/southbridge/via/k8t890/host.c +++ b/src/southbridge/via/k8t890/host.c @@ -60,7 +60,7 @@ static void host_enable(struct device *dev) /* Multiple function control */ pci_write_config8(dev, K8T890_MULTIPLE_FN_EN, 0x01);
- print_debug(" VIA_X_0 device dump:\n"); + printk(BIOS_DEBUG, " VIA_X_0 device dump:\n"); dump_south(dev); }
diff --git a/src/southbridge/via/k8t890/host_ctrl.c b/src/southbridge/via/k8t890/host_ctrl.c index 74351bc..2f4bca7 100644 --- a/src/southbridge/via/k8t890/host_ctrl.c +++ b/src/southbridge/via/k8t890/host_ctrl.c @@ -84,7 +84,7 @@ static void host_ctrl_enable_k8t8xx(struct device *dev) writeback(dev, 0xc4, 0x50); writeback(dev, 0xc5, 0x50);
- print_debug(" VIA_X_2 device dump:\n"); + printk(BIOS_DEBUG, " VIA_X_2 device dump:\n"); dump_south(dev); }
diff --git a/src/southbridge/via/vt8237r/ctrl.c b/src/southbridge/via/vt8237r/ctrl.c index 3d856a8..f951afa 100644 --- a/src/southbridge/via/vt8237r/ctrl.c +++ b/src/southbridge/via/vt8237r/ctrl.c @@ -130,7 +130,7 @@ static void vt8237s_vlink_init(struct device *dev) /* No pairing NB was found. */ if (!devfun7) { - print_debug("vt8237s_vlink_init: No pairing NB was found.\n"); + printk(BIOS_DEBUG, "vt8237s_vlink_init: No pairing NB was found.\n"); return; }
@@ -205,7 +205,7 @@ static void vt8237a_vlink_init(struct device *dev) /* No pairing NB was found. */ if (!devfun7) { - print_debug("vt8237a_vlink_init: No pairing NB was found.\n"); + printk(BIOS_DEBUG, "vt8237a_vlink_init: No pairing NB was found.\n"); return; }
diff --git a/src/southbridge/via/vt8237r/early_smbus.c b/src/southbridge/via/vt8237r/early_smbus.c index 747dc5c..bb06322 100644 --- a/src/southbridge/via/vt8237r/early_smbus.c +++ b/src/southbridge/via/vt8237r/early_smbus.c @@ -42,17 +42,17 @@ static void smbus_print_error(u8 host_status, int loops) return;
if (loops >= SMBUS_TIMEOUT) - print_err("SMBus timeout\n"); + printk(BIOS_ERR, "SMBus timeout\n"); if (host_status & (1 << 4)) - print_err("Interrupt/SMI# was Failed Bus Transaction\n"); + printk(BIOS_ERR, "Interrupt/SMI# was Failed Bus Transaction\n"); if (host_status & (1 << 3)) - print_err("Bus error\n"); + printk(BIOS_ERR, "Bus error\n"); if (host_status & (1 << 2)) - print_err("Device error\n"); + printk(BIOS_ERR, "Device error\n"); if (host_status & (1 << 1)) - print_debug("Interrupt/SMI# completed successfully\n"); + printk(BIOS_DEBUG, "Interrupt/SMI# completed successfully\n"); if (host_status & (1 << 0)) - print_err("Host busy\n"); + printk(BIOS_ERR, "Host busy\n"); }
/** @@ -229,7 +229,7 @@ void smbus_fixup(const struct mem_controller *ctrl)
ram_slots = ARRAY_SIZE(ctrl->channel0); if (!ram_slots) { - print_err("smbus_fixup() thinks there are no RAM slots!\n"); + printk(BIOS_ERR, "smbus_fixup() thinks there are no RAM slots!\n"); return; }
@@ -253,7 +253,7 @@ void smbus_fixup(const struct mem_controller *ctrl) }
if (i >= SMBUS_TIMEOUT) - print_err("SMBus timed out while warming up\n"); + printk(BIOS_ERR, "SMBus timed out while warming up\n"); else PRINT_DEBUG("Done\n"); } @@ -336,7 +336,7 @@ int acpi_is_wakeup_early(void) device_t dev; u16 tmp;
- print_debug("IN TEST WAKEUP\n"); + printk(BIOS_DEBUG, "IN TEST WAKEUP\n");
/* Power management controller */ dev = get_vt8237_lpc(); @@ -351,7 +351,7 @@ int acpi_is_wakeup_early(void)
tmp = inw(VT8237R_ACPI_IO_BASE + 0x04);
- print_debug_hex8(tmp); + printk(BIOS_DEBUG, "%02x", tmp); return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; } #endif @@ -426,7 +426,7 @@ int vt8237_early_network_init(struct vt8237_network_rom *rom) dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_7), 0); if (dev == PCI_DEV_INVALID) { - print_err("Network is disabled, please enable\n"); + printk(BIOS_ERR, "Network is disabled, please enable\n"); return 0; }
@@ -441,7 +441,7 @@ int vt8237_early_network_init(struct vt8237_network_rom *rom) return 0;
if (rom == NULL) { - print_err("No config data specified, using default MAC!\n"); + printk(BIOS_ERR, "No config data specified, using default MAC!\n"); n.mac_address[0] = 0x0; n.mac_address[1] = 0x0; n.mac_address[2] = 0xde; @@ -503,7 +503,7 @@ int vt8237_early_network_init(struct vt8237_network_rom *rom) }
if (loops >= LAN_TIMEOUT) { - print_err("Timeout - LAN controller didn't accept config\n"); + printk(BIOS_ERR, "Timeout - LAN controller didn't accept config\n"); return 0; }
diff --git a/src/southbridge/via/vt8237r/vt8237r.c b/src/southbridge/via/vt8237r/vt8237r.c index 5f2449a..d392512 100644 --- a/src/southbridge/via/vt8237r/vt8237r.c +++ b/src/southbridge/via/vt8237r/vt8237r.c @@ -37,13 +37,9 @@ void writeback(struct device *dev, u16 where, u8 what) pci_write_config8(dev, where, what); regval = pci_read_config8(dev, where);
- if (regval != what) { - print_debug("Writeback to "); - print_debug_hex8(where); - print_debug(" failed "); - print_debug_hex8(regval); - print_debug("\n"); - } + if (regval != what) + printk(BIOS_DEBUG, "Writeback to %02x failed %02x\n", + where, regval); } #else void writeback(struct device *dev, u16 where, u8 what) diff --git a/src/southbridge/via/vt8237r/vt8237r.h b/src/southbridge/via/vt8237r/vt8237r.h index ee5cc82..8c7ae45 100644 --- a/src/southbridge/via/vt8237r/vt8237r.h +++ b/src/southbridge/via/vt8237r/vt8237r.h @@ -94,8 +94,8 @@ #define CLOCK_SLAVE_ADDRESS 0x69
#if CONFIG_DEBUG_SMBUS -#define PRINT_DEBUG(x) print_debug(x) -#define PRINT_DEBUG_HEX16(x) print_debug_hex16(x) +#define PRINT_DEBUG(x) printk(BIOS_DEBUG, x) +#define PRINT_DEBUG_HEX16(x) printk(BIOS_DEBUG, "%04x", x) #else #define PRINT_DEBUG(x) #define PRINT_DEBUG_HEX16(x)