[coreboot-gerrit] Change in coreboot[master]: AGESA, binaryPI: implement C bootblock

[Michał Żygowski (Code Review)]

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36914 )

Change subject: AGESA, binaryPI: implement C bootblock
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Patch Set 31:

(1 comment)

https://review.coreboot.org/c/coreboot/+/36914/28/src/drivers/amd/agesa/boot... 
File src/drivers/amd/agesa/bootblock.c:

https://review.coreboot.org/c/coreboot/+/36914/28/src/drivers/amd/agesa/boot... 
PS28, Line 40: 	set_var_mtrr(mtrr, OPTIMAL_CACHE_ROM_BASE, OPTIMAL_CACHE_ROM_SIZE,
> Somehow I was thinking this is calling get_free_var_mtrr() while it clearly is not doing that. […]

I have originated this code for amd_initmmio from fixme.c files. These settings are shared across all families in AGESA and binaryPI, i.e. ROM caching is configured with 7th MTRR base/mask pair for all of them.