Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37895 )
Change subject: arch/x86: Top align bootblock program ......................................................................
arch/x86: Top align bootblock program
Change-Id: If32518b1c19d08935727330314904b52a246af3c Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/arch/x86/bootblock_crt0.S M src/arch/x86/memlayout.ld D src/arch/x86/prologue.inc M src/arch/x86/walkcbfs.S M src/cpu/intel/car/core2/cache_as_ram.S M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/p3/cache_as_ram.S M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/intel/microcode/microcode_asm.S M src/cpu/x86/16bit/entry16.inc M src/cpu/x86/16bit/reset16.ld M src/drivers/amd/agesa/cache_as_ram.S M src/soc/amd/common/block/cpu/car/cache_as_ram.S 13 files changed, 68 insertions(+), 30 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/37895/1
diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S index 3256731..d4dbf28 100644 --- a/src/arch/x86/bootblock_crt0.S +++ b/src/arch/x86/bootblock_crt0.S @@ -25,7 +25,9 @@ * Include the old code for reset vector and protected mode entry. That code has * withstood the test of time. */ -#include <arch/x86/prologue.inc> + +.section ".bootblock.top", "ax", @progbits + #include <cpu/x86/16bit/entry16.inc> #include <cpu/x86/16bit/reset16.inc> #include <cpu/x86/32bit/entry32.inc> @@ -69,3 +71,5 @@
/* We're done. Now it's up to platform-specific code */ jmp bootblock_pre_c_entry + +.previous diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index eff3738..38c4664 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -49,8 +49,6 @@
#include EARLY_MEMLAYOUT #elif ENV_BOOTBLOCK - BOOTBLOCK(CONFIG_X86_RESET_VECTOR - CONFIG_C_ENV_BOOTBLOCK_SIZE + 0x10, - CONFIG_C_ENV_BOOTBLOCK_SIZE)
#include EARLY_MEMLAYOUT
diff --git a/src/arch/x86/prologue.inc b/src/arch/x86/prologue.inc deleted file mode 100644 index 4036ff9..0000000 --- a/src/arch/x86/prologue.inc +++ /dev/null @@ -1,17 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cpu/x86/post_code.h> - -.section ".rom.data", "a", @progbits -.section ".rom.text", "ax", @progbits diff --git a/src/arch/x86/walkcbfs.S b/src/arch/x86/walkcbfs.S index ded6558..82fd077 100644 --- a/src/arch/x86/walkcbfs.S +++ b/src/arch/x86/walkcbfs.S @@ -31,7 +31,7 @@
#define CBFS_FILE_STRUCTSIZE (CBFS_FILE_OFFSET + 4)
-.section .text +.section ".bootblock.top" .global walkcbfs_asm
/* @@ -131,3 +131,5 @@
filemagic: .ascii "LARCHIVE" + +.previous diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index 73618d9..65db322 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -23,6 +23,7 @@ #endif #define XIP_ROM_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE
+.section ".bootblock.top" .global bootblock_pre_c_entry
.code32 @@ -210,3 +211,4 @@ fixed_mtrr_list_size = . - fixed_mtrr_list
_cache_as_ram_setup_end: +.previous diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index 4dee0a8..00e7b4f 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -22,6 +22,7 @@ #define NoEvictMod_MSR 0x2e0 #define BBL_CR_CTL3_MSR 0x11e
+.section ".bootblock.top" .global bootblock_pre_c_entry
.code32 @@ -254,3 +255,4 @@ fixed_mtrr_list_size = . - fixed_mtrr_list
_cache_as_ram_setup_end: +.previous diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S index 5262b18..94540ca 100644 --- a/src/cpu/intel/car/p3/cache_as_ram.S +++ b/src/cpu/intel/car/p3/cache_as_ram.S @@ -23,6 +23,7 @@ #endif #define XIP_ROM_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE
+.section ".bootblock.top" .global bootblock_pre_c_entry
.code32 @@ -198,3 +199,4 @@ fixed_mtrr_list_size = . - fixed_mtrr_list
_cache_as_ram_setup_end: +.previous diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index fdeb0af..8a21b48 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -27,6 +27,7 @@ #endif #define XIP_ROM_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE
+.section ".bootblock.top" .global bootblock_pre_c_entry
.code32 @@ -409,3 +410,4 @@ fixed_mtrr_list_size = . - fixed_mtrr_list
_cache_as_ram_setup_end: +.previous diff --git a/src/cpu/intel/microcode/microcode_asm.S b/src/cpu/intel/microcode/microcode_asm.S index 647f67c..2458185 100644 --- a/src/cpu/intel/microcode/microcode_asm.S +++ b/src/cpu/intel/microcode/microcode_asm.S @@ -54,7 +54,7 @@ * if the revision of the update is newer than what is installed */
-.section .text +.section ".bootblock.top" .global update_bsp_microcode
update_bsp_microcode: @@ -162,3 +162,5 @@ .string "cpu_microcode_blob.bin"
_update_bsp_microcode_end: + +.previous diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index 40c0e99..b1aaa10 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -28,11 +28,11 @@ */
#include <arch/rom_segs.h> +#include <cpu/x86/post_code.h>
-/* Symbol _start16bit must be aligned to 4kB to start AP CPUs with - * Startup IPI message without RAM. +/* Symbol _start16bit must reachable from the reset vector, and be aligned to + * 4kB to start AP CPUs with Startup IPI message without RAM. */ -.align 4096 .code16 .globl _start16bit .type _start16bit, @function diff --git a/src/cpu/x86/16bit/reset16.ld b/src/cpu/x86/16bit/reset16.ld index ec01810..56672e8 100644 --- a/src/cpu/x86/16bit/reset16.ld +++ b/src/cpu/x86/16bit/reset16.ld @@ -14,9 +14,35 @@ /* _RESET_VECTOR: typically the top of the ROM */
SECTIONS { - /* Trigger an error if I have an unuseable start address */ - _TOO_LOW = CONFIG_X86_RESET_VECTOR - 0xfff0; - _bogus = ASSERT(_start16bit >= _TOO_LOW, "_start16bit too low. Please report."); + + /* + * Symbol ap_sipi_vector must be aligned to 4kB to start AP CPUs + * with Startup IPI message without RAM. Align .rom to next 4 byte + * boundary anyway. + */ + + .bogus ROMLOC_MIN : { + . = ALIGN(4); + } + + INCLUDE "bootblock/lib/program.ld" + + .bootblock_top . : { + . = CONFIG(SIPI_VECTOR_IN_ROM) ? ALIGN(4096) : ALIGN(4); + _realmode = .; + *(.bootblock.top); + _erealmode = .; + } + + PROGRAM_SZ = (_eprogram - _program + 16); + EARLYASM_SZ = (_erealmode - _realmode + 16) + (CONFIG(SIPI_VECTOR_IN_ROM) ? 4096 : 0); + + /* + * Allocation reserves extra 16 bytes here. Alignment requirements + * may cause the total size of a section to change when the start + * address gets applied. + */ + ROMLOC_MIN = CONFIG_X86_RESET_VECTOR - 0xf0 - (PROGRAM_SZ + EARLYASM_SZ);
. = CONFIG_X86_RESET_VECTOR; .reset . : { diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index 1034992..d436805 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -21,16 +21,19 @@ ****************************************************************************** */
-#include "gcccar.inc" #include <cpu/x86/lapic_def.h> #include <cpu/x86/post_code.h>
+.section ".bootblock.top" + .code32 .globl _cache_as_ram_setup, _cache_as_ram_setup_end .global bootblock_pre_c_entry
_cache_as_ram_setup:
+#include "gcccar.inc" + /* * on entry: * mm0: BIST (ignored) @@ -84,3 +87,4 @@ jmp stop
_cache_as_ram_setup_end: +.previous diff --git a/src/soc/amd/common/block/cpu/car/cache_as_ram.S b/src/soc/amd/common/block/cpu/car/cache_as_ram.S index 402da3a..e64b6d2 100644 --- a/src/soc/amd/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/amd/common/block/cpu/car/cache_as_ram.S @@ -21,10 +21,18 @@ ****************************************************************************** */
-#include "gcccar.inc" #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h>
+.section ".bootblock.top" + +.code32 +.globl _cache_as_ram_setup, _cache_as_ram_setup_end + +_cache_as_ram_setup: + +#include "gcccar.inc" + /* * on entry: * mm0: BIST (ignored) @@ -57,3 +65,6 @@ post_code(POST_DEAD_CODE) hlt jmp .halt_forever + +_cache_as_ram_setup_end: +.previous