Attention is currently required from: Patrick Rudolph.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78228?usp=email )
Change subject: sb/intel/bd82x6x: Improve SLCAP ......................................................................
Patch Set 2:
(1 comment)
File src/southbridge/intel/bd82x6x/pcie.c:
https://review.coreboot.org/c/coreboot/+/78228/comment/9422b864_7444f48c : PS2, Line 152: reg32 |= (slot_number++ << 19);
The SI Slot Implemented flag is now always set for enabled or hot pluggable ports, thus the check wo […]
Yes, I left a request on another commit to leave a comment that we don't follow the specs when we unconditionally set (or do not clear) SI bit for upstream links of integrated devices.
If the spec says SLTCAP must be implemented when SI is set, it implies it may not be implemented otherwise. I had a look at pciutils/lspci source, seemed like it does not parse or print SLTCAP when SI=0.
I'd still like the first slot_number to be programmed with PSN=1 to make it unique from the SLTCAP registers that default to PSN=0 and are not programmed at all.