Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48286 )
Change subject: src/soc/intel: Add support for CAR_HAS_SF_MASKS and select for TGL ......................................................................
Patch Set 17:
(2 comments)
https://review.coreboot.org/c/coreboot/+/48286/17/src/soc/intel/common/block... File src/soc/intel/common/block/cpu/car/exit_car.S:
https://review.coreboot.org/c/coreboot/+/48286/17/src/soc/intel/common/block... PS17, Line 101: CONFIG_IA32_L3_MASK_1_DEFAULT
Since this is used by all soc/intel/ platforms, what is getting programmed here for platforms other […]
If we don't have the values for other platforms yet, then this needs to be guarded by CONFIG_SOC_INTEL_TIGERLAKE
https://review.coreboot.org/c/coreboot/+/48286/17/src/soc/intel/tigerlake/Kc... File src/soc/intel/tigerlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/48286/17/src/soc/intel/tigerlake/Kc... PS17, Line 255: 0xffff
Isn't the default mask dependent on number of ways?
The eNEM programming instructions said to set these MSRs back to their reset default values, which came from the EDS; I didn't say any special notes about the reset value being dependent on the cache size