Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36625 )
Change subject: Documentation: Add some significant 4.11 release notes ......................................................................
Documentation: Add some significant 4.11 release notes
Change-Id: Ia881cfa9382d0b2fa2652696b912030af942b68a Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/36625 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz Reviewed-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M Documentation/releases/coreboot-4.11-relnotes.md 1 file changed, 19 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved Arthur Heymans: Looks good to me, approved
diff --git a/Documentation/releases/coreboot-4.11-relnotes.md b/Documentation/releases/coreboot-4.11-relnotes.md index 7dd99a3..38299c1 100644 --- a/Documentation/releases/coreboot-4.11-relnotes.md +++ b/Documentation/releases/coreboot-4.11-relnotes.md @@ -40,3 +40,22 @@
Significant refactoring has bee done to achieve some consistency across platforms and to reduce code duplication. + +### Added VBOOT support to the following platforms: +* intel/gm45 +* intel/nehalem + +### Moved the following platforms to C_ENVIRONMENT_BOOTBLOCK: +* intel/gm45 +* intel/nehalem +* intel/braswell + +### Other +* Did cleanups around TSC timer +* Improved automatic VR configuration on SKL/KBL +* Filled additional fields in SMBIOS type 4 +* Removed magic value replay from Intel Nehalem/ibexpeak code base +* Added OpenSBI on RISCV platforms +* Did more preparations for Intel TXT support +* Did more preparations for x86_64 stage support +* Added SSDT generator for arbitrary SuperIO chips based on devicetree.cb