Attention is currently required from: Andrey Petrov, Ronak Kanabar, Subrata Banik.
Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80691?usp=email )
Change subject: drivers/intel/fsp2_0: Initialize CPUs only when FSP-S has completed ......................................................................
Patch Set 2: -Code-Review
(1 comment)
Patchset:
PS2: I've been looking into this CL issue on Meteor Lake rex. It turns out that the error I was running into is the result of Chrome FSP ebuild recipe stripping down the FSP binary and removing the MP service support in the process. If I use a non-stripped version of the FSP it boots way further. However, it still fails:
[DEBUG] Setting up SMI for CPU [DEBUG] IED base = 0x77400000 [DEBUG] IED size = 0x00400000 [INFO ] Will perform SMM setup. [INFO ] CPU: Genuine Intel(R) 0000. [EMERG] Switching from X2APIC to XAPIC mode is not implemented.
This seems to be the result of an incompatibility between what has been programmed by the FSP and coreboot expectation. It seems that `USE_INTEL_FSP_MP_INIT` use-case is not really supported on Meteor Lake rex unless PPI are passed to FSP.
**Note** that I also verified that this CL works fine on Raptor Lake brya0 board which uses `USE_INTEL_FSP_MP_INIT` by default.