[coreboot-gerrit] Change in coreboot[master]: mb/google/dedede: Add memory initialization support for dedede

[Karthik Ramasubramanian (Code Review)]

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39136 )

Change subject: mb/google/dedede: Add memory initialization support for dedede
......................................................................

Patch Set 25:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39136/25/src/mainboard/google/deded... 
File src/mainboard/google/dedede/variants/waddledoo/memory.c:

https://review.coreboot.org/c/coreboot/+/39136/25/src/mainboard/google/deded... 
PS25, Line 41: 1, 3, 0, 2, 7, 5, 4, 6
> I checked again in schematics the mapping is correct.

Synced up with Aamir offline. My understanding was that the index in the array corresponds to DRAM's DQS ID and the value in the array corresponds to CPU's DQS ID. This is documented that way for all the SoCs like CNL and TGL. Hence I came with that array definition. Also the comment above the array says so.

Aamir mentioned to me that the index in the array corresponds to CPU's DQS ID and the value in the array corresponds to DRAM's DQS ID. If so, then the array definition matches with the schematics. Probably the documentation shared for previous SoCs needs to be fixed?