Hello Kyösti Mälkki, Werner Zeh, Patrick Rudolph, build bot (Jenkins), Aaron Durbin, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33775
to look at the new patch set (#2).
Change subject: soc/{amd, intel}: Increase size of postcar stack ......................................................................
soc/{amd, intel}: Increase size of postcar stack
If you currently activate the measured boot on an Apollo Lake mainboard, you will run into a stack overflow during postcar. Such a behavior has already been observed on the Sky Lake platform and a corresponding patch has been made for this (https://review.coreboot.org/c/coreboot/+/33434). This issue occurs since the patch for the correct timestamp value in postcar comes up (https://review.coreboot.org/c/coreboot/+/32726 and https://review.coreboot.org/c/coreboot/+/32881). By increasing the stack size for postcar the issue is solved.
This patch adds a general define for it and sets the value to 4KiB. All platforms that have used less than this 4KiB so far will be adjusted to the new value. This value should be the lowest limit for the postcar stack size.
Change-Id: Iba1fb5bfad6946f316feac2d8c998a782142a56a Signed-off-by: Mario Scheithauer mario.scheithauer@siemens.com --- M src/include/memlayout.h M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/cannonlake/romstage/romstage.c M src/soc/intel/denverton_ns/romstage.c M src/soc/intel/icelake/romstage/romstage.c M src/soc/intel/quark/romstage/fsp2_0.c 7 files changed, 25 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/33775/2