9 Apr
2023
9 Apr
'23
1:58 a.m.
Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held.
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74288 )
Change subject: soc/amd/common/blk/pcie: Program LTR max latencies ......................................................................
Patch Set 1:
(1 comment)
File src/soc/amd/common/block/pci/pcie_gpp.c:
https://review.coreboot.org/c/coreboot/+/74288/comment/5284c59f_df5a0c3d PS1, Line 51: PCIE_LTR_MAX_LATENCY_1047US How was this value determined?
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Gerrit-Project: coreboot
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Gerrit-Change-Id: Icf188e69cf5676be870873c56d175423d16704b4
Gerrit-Change-Number: 74288
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