Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41224 )
Change subject: mb/asus/.../p3b-f: Enable flashrom in ramstage final ......................................................................
mb/asus/.../p3b-f: Enable flashrom in ramstage final
p3b-f needs a special (but known) trick for flashrom to work. as that trick no longer works after introducing ACPI support, add a mainboard finalize hook to do it at the end of ramstage.
Ideally this would be controlled by an nvram option.
TEST=flashrom detects flash chip without further user action.
Change-Id: I684f8f560a714cbcaf56033202a841e6801ad999 Signed-off-by: Keith Hui buurin@gmail.com --- M src/mainboard/asus/p2b/Makefile.inc A src/mainboard/asus/p2b/variants/p3b-f/mainboard.c 2 files changed, 30 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/41224/1
diff --git a/src/mainboard/asus/p2b/Makefile.inc b/src/mainboard/asus/p2b/Makefile.inc index eb48944..5b936cb 100644 --- a/src/mainboard/asus/p2b/Makefile.inc +++ b/src/mainboard/asus/p2b/Makefile.inc @@ -1,5 +1,6 @@ bootblock-y += bootblock.c romstage-$(CONFIG_BOARD_ASUS_P3B_F) += variants/$(VARIANT_DIR)/romstage.c +ramstage-$(CONFIG_BOARD_ASUS_P3B_F) += variants/$(VARIANT_DIR)/mainboard.c
ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += variants/$(VARIANT_DIR)/irq_tables.c ramstage-$(CONFIG_GENERATE_MP_TABLE) += variants/$(VARIANT_DIR)/mptable.c diff --git a/src/mainboard/asus/p2b/variants/p3b-f/mainboard.c b/src/mainboard/asus/p2b/variants/p3b-f/mainboard.c new file mode 100644 index 0000000..f2d322f --- /dev/null +++ b/src/mainboard/asus/p2b/variants/p3b-f/mainboard.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <device/smbus_host.h> +#include <device/pci_ops.h> +#include <console/console.h> +#include <southbridge/intel/i82371eb/i82371eb.h> + +/** + * Finalize mainboard. For p3b-f, attempt to enable flashrom. + * @param chip_info Ignored + */ +static void mainboard_final(void *chip_info) +{ + const pci_devfn_t px43 = PCI_DEV(0, 4, 3); + int r; + uintptr_t base; + base = pci_s_read_config32(px43, SMBBA) & 0xfff0; + + printk(BIOS_INFO, "Flashrom enable"); + r = do_smbus_write_byte(base, 0x48, 0x80, 0x80); + if (r < 0) + printk(BIOS_INFO," faile"); + printk(BIOS_INFO,"d\n"); +} + +struct chip_operations mainboard_ops = { + .final = mainboard_final +};