[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Set correct temperature threshold for PCH Therm...

[Sumeet R Pawnikar (Code Review)]

Hello Aaron Durbin, Rajat Jain, Paul Fagerburg, Tim Wawrzynczak, Duncan Laurie, Shelley Chen, build bot (Jenkins), Furquan Shaikh, Patrick Georgi,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/33129

to look at the new patch set (#4).

Change subject: soc/intel/cannonlake: Set correct temperature threshold for PCH Thermal Sensor
......................................................................

soc/intel/cannonlake: Set correct temperature threshold for PCH Thermal Sensor

PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and
DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal shutdown
when S0ix is enabled.

BUG=None
BRANCH=None
TEST=Verified Thermal Device (B0: D18: F0) TSPM offset 0x1c [LTT (8:0)]
value is 0xFA.

Change-Id: Ibd1e669fcbfe8dc6e6e5556aa5b1373ed19c3685
Signed-off-by: Sumeet Pawnikar 
---
M src/soc/intel/cannonlake/Makefile.inc
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/finalize.c
M src/soc/intel/cannonlake/include/soc/iomap.h
A src/soc/intel/cannonlake/include/soc/thermal.h
A src/soc/intel/cannonlake/thermal.c
6 files changed, 148 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/33129/4