Attention is currently required from: Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Michael Niewöhner, EricR Lai.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Refactor PCIE port config
......................................................................
Patch Set 64:
(1 comment)
File src/mainboard/intel/adlrvp/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/48340/comment/d6599ec3_6ab32362
PS59, Line 58: # Clock source is shared with LAN and hence marked as free running.
Subrata, can you please provide the dump of PCIe related UPDs: […]
Verified all PCIE devices are working with this patch trend
----------------- PCH PCIe RP PreMem Config ------------------
Port[0] RpEnabled= 1
Port[1] RpEnabled= 0
Port[2] RpEnabled= 1
Port[3] RpEnabled= 1
Port[4] RpEnabled= 1
Port[5] RpEnabled= 1
Port[6] RpEnabled= 0
Port[7] RpEnabled= 1
Port[8] RpEnabled= 1
Port[9] RpEnabled= 0
Port[10] RpEnabled= 1
Port[11] RpEnabled= 0
Clock[0] Usage= 40
Clock[0] ClkReq= 0
Clock[1] Usage= 8
Clock[1] ClkReq= 1
Clock[2] Usage= 4
Clock[2] ClkReq= 2
Clock[3] Usage= 41
Clock[3] ClkReq= 3
Clock[4] Usage= 42
Clock[4] ClkReq= 4
Clock[5] Usage= 5
Clock[5] ClkReq= 5
Clock[6] Usage= 80
Clock[6] ClkReq= FF
Clock[7] Usage= 0
Clock[7] ClkReq= FF
Clock[8] Usage= 0
Clock[8] ClkReq= FF
Clock[9] Usage= 0
Clock[9] ClkReq= FF
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