[coreboot-gerrit] Change in coreboot[master]: nb/intel/ironlake: Drop `heci_bar` field from raminit

[Angel Pons (Code Review)]

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45361 )

Change subject: nb/intel/ironlake: Drop `heci_bar` field from raminit
......................................................................

nb/intel/ironlake: Drop `heci_bar` field from raminit

This field is only written to, never read. Drop it from raminfo.
Also, bump MRC_CACHE_VERSION as the saved data layout has changed.

Change-Id: I83d6e69addff996e2f18472d3e1d4f7b9ba974fd
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45361
Tested-by: build bot (Jenkins) 
Reviewed-by: Arthur Heymans 
---
M src/northbridge/intel/ironlake/raminit.c
1 file changed, 1 insertion(+), 7 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Arthur Heymans: Looks good to me, approved

diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c
index 5d58b27..46fb74d 100644
--- a/src/northbridge/intel/ironlake/raminit.c
+++ b/src/northbridge/intel/ironlake/raminit.c
@@ -61,7 +61,7 @@
    u8 largest;
 } timing_bounds_t[2][2][2][9];

-#define MRC_CACHE_VERSION 1
+#define MRC_CACHE_VERSION 2

struct ram_training {
    /* [TM][CHANNEL][SLOT][RANK][LANE] */
@@ -192,7 +192,6 @@
    unsigned int interleaved_part_mb;
    unsigned int non_interleaved_part_mb;

-	u32 heci_bar;
    u64 heci_uma_addr;
    unsigned int memory_reserved_for_heci_mb;

@@ -1469,9 +1468,6 @@
    while (!(read8((u8 *)0xfed40000) & (1 << 7)))
    	;

-	if (!info->heci_bar)
-		gav(info->heci_bar =
-		    pci_read_config32(HECIDEV, HECIBAR) & 0xFFFFFFF8);
    if (!info->memory_reserved_for_heci_mb) {
    	/* Wait for ME to be ready */
    	intel_early_me_init();
@@ -1817,7 +1813,6 @@
    if (!((reg44 & 0x10000) && !(pci_read_config32(HECIDEV, 0x40) & 0x20)))
    	return;

-	info->heci_bar = pci_read_config32(HECIDEV, 0x10) & 0xFFFFFFF0;
    info->memory_reserved_for_heci_mb = reg44 & 0x3f;
    info->heci_uma_addr =
        ((u64)
@@ -3727,7 +3722,6 @@
    info.training.reg_178 = 0;
    info.training.reg_10b = 0;

-	info.heci_bar = 0;
    info.memory_reserved_for_heci_mb = 0;

/* before SPD */