[coreboot-gerrit] Change in coreboot[master]: mb/siemens/mc_apl6: Enable eMMC and program eMMC DLL settings

[Mario Scheithauer (Code Review)]

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45898 )

Change subject: mb/siemens/mc_apl6: Enable eMMC and program eMMC DLL settings
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mb/siemens/mc_apl6: Enable eMMC and program eMMC DLL settings

Enable eMMC and program eMMC DLL settings for mc_apl6 mainboard.

Change-Id: Ib760a1a26a92047e8916979ffb5001bcff0a6e45
Signed-off-by: Mario Scheithauer 
---
M src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
1 file changed, 48 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/45898/1

diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
index 4aa8bc9..e9fd143 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
@@ -14,6 +14,53 @@
    register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
    register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"

+	# EMMC TX CMD Delay
+	# Refer to EDS-Vol2-21.3.7
+	# [14:8] steps of delay for HS400, each 125ps.
+	# [6:0]  steps of delay for SDR104/HS200, each 125ps.
+	# SDR Mode 3h - 375ps
+	register "emmc_tx_cmd_cntl" = "0x00000503"
+
+	# EMMC TX DATA Delay 1
+	# Refer to EDS-Vol2-21.3.8
+	# [14:8] steps of delay for HS400, each 125ps.
+	# [6:0] steps of delay for SDR104/HS200, each 125ps.
+	# HS200 Mode Bh - 1.375ns
+	register "emmc_tx_data_cntl1" = "0x0C0B"
+
+	# EMMC TX DATA Delay 2
+	# Refer to EDS-Vol2-21.3.9
+	# [30:24] steps of delay for SDR50, each 125ps.
+	# [22:16] steps of delay for DDR50, each 125ps.
+	# [14:8] steps of delay for SDR25/HS50, each 125ps.
+	# [6:0] steps of delay for SDR12, each 125ps.
+	register "emmc_tx_data_cntl2" = "0x28162828"
+
+	# EMMC RX CMD/DATA Delay 1
+	# Refer to EDS-Vol2-21.3.10
+	# [30:24] steps of delay for SDR50, each 125ps.
+	# [22:16] steps of delay for DDR50, each 125ps.
+	# [14:8] steps of delay for SDR25/HS50, each 125ps.
+	# [6:0] steps of delay for SDR12, each 125ps.
+	register "emmc_rx_cmd_data_cntl1" = "0x00181717"
+
+	# EMMC RX Strobe Ctrl
+	# Refer to EDS-Vol2-21.3.11
+	# [14:8] hs400_mode1: Rx Strobe Delay DLL 1 (HS400 Mode)
+	# [6:0] hs400_mode2: Rx Strobe Delay DLL 2 (HS400 Mode)
+	register "emmc_rx_strobe_cntl" = "0xa0a"
+
+	# EMMC RX CMD/DATA Delay 2
+	# Refer to EDS-Vol2-21.3.12
+	# [17:16] stands for Rx Clock before Output Buffer
+	# [14:8] steps of delay for Auto Tuning Mode, each 125ps.
+	# [6:0] steps of delay for HS200, each 125ps.
+	# HS200 Mode 4h - 500ps
+	register "emmc_rx_cmd_data_cntl2" = "0x10004"
+
+	# 0:HS400(Default), 1:HS200, 2:DDR50
+	register "emmc_host_max_speed" = "1"
+
    # Enable Vtd feature
    register "enable_vtd" = "1"

@@ -70,7 +117,7 @@
    	device pci 19.2 off end	# - SPI 2
    	device pci 1a.0 off end	# - PWM
    	device pci 1b.0 on  end	# - SDCARD
-		device pci 1c.0 off end	# - eMMC
+		device pci 1c.0 on  end	# - eMMC
    	device pci 1d.0 off end	# - UFS
    	device pci 1e.0 off end	# - SDIO
    	device pci 1f.0 on	# - LPC