[coreboot-gerrit] Change in coreboot[master]: mc_bdx1: Enable UART for GDB debugging

[Werner Zeh (Code Review)]

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36023 )

Change subject: mc_bdx1: Enable UART for GDB debugging
......................................................................

mc_bdx1: Enable UART for GDB debugging

Change-Id: I724402b51295be85500a79e21a4379ed43903e26
Signed-off-by: Werner Zeh 
---
M src/mainboard/siemens/mc_bdx1/romstage.c
1 file changed, 43 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/36023/1

diff --git a/src/mainboard/siemens/mc_bdx1/romstage.c b/src/mainboard/siemens/mc_bdx1/romstage.c
index eec8f04..8051200 100644
--- a/src/mainboard/siemens/mc_bdx1/romstage.c
+++ b/src/mainboard/siemens/mc_bdx1/romstage.c
@@ -20,7 +20,47 @@
 #include <drivers/intel/fsp1_0/fsp_util.h>
 #include <soc/gpio.h>
 #include "gpio.h"
+#if IS_ENABLED(CONFIG_GDB_STUB)
+#include <device/device.h>
+#include <device/pci.h>
+#include <arch/io.h>

+#define FPGA_PCI_BUS		1
+#define FPGA_TEMP_BAR0		0xf7000000
+
+
+static void mainbaord_enable_gdb_stub(void)
+{
+	uint32_t reg;
+
+	/* First set up root port bridge to get access to the FPGA. */
+	/* Set secondary bus temporary. */
+	pci_write_config32(PCI_DEV(0, 0x1c, 0x03), PCI_PRIMARY_BUS,
+			FPGA_PCI_BUS << 16 | FPGA_PCI_BUS << 8);
+	/* Define an address window to forward to the secondary bus. */
+	pci_write_config32(PCI_DEV(0, 0x1c, 0x03), PCI_MEMORY_BASE,
+			(FPGA_TEMP_BAR0 | (FPGA_TEMP_BAR0 >> 16)));
+	/* Enable memory mapped transfers */
+	pci_write_config32(PCI_DEV(0, 0x1c, 0x03), PCI_COMMAND,
+				PCI_COMMAND_MEMORY);
+	/* Now the FPGA is visible on bus 1, dev 0, function 0. */
+	pci_write_config32(PCI_DEV(FPGA_PCI_BUS, 0, 0), PCI_BASE_ADDRESS_0,
+				FPGA_TEMP_BAR0);
+	pci_write_config32(PCI_DEV(FPGA_PCI_BUS, 0, 0), PCI_COMMAND,
+				PCI_COMMAND_MEMORY);
+	/* Now we can reach MMIO mapped registers in CUPER */
+	reg = read32((void *)(FPGA_TEMP_BAR0 + 0xbc));
+	reg |= (1 << 10);
+	write32((void *)(FPGA_TEMP_BAR0 + 0xbc), reg);
+	/* Now delete all the changes made in config space so that
+	   the PCI enumerator can do it's work. */
+	pci_write_config32(PCI_DEV(FPGA_PCI_BUS, 0, 0), PCI_BASE_ADDRESS_0, 0);
+	pci_write_config32(PCI_DEV(FPGA_PCI_BUS, 0, 0), PCI_COMMAND, 0);
+	pci_write_config32(PCI_DEV(0, 0x1c, 0x03), PCI_PRIMARY_BUS, 0x0);
+	pci_write_config32(PCI_DEV(0, 0x1c, 0x03), PCI_MEMORY_BASE, 0);
+	pci_write_config32(PCI_DEV(0, 0x1c, 0x03), PCI_COMMAND, 0);
+}
+#endif
 /**
  * /brief mainboard call for setup that needs to be done before fsp init
  *
@@ -36,7 +76,9 @@
  */
 void late_mainboard_romstage_entry(void)
 {
-
+#if (IS_ENABLED(CONFIG_GDB_STUB))
+	mainbaord_enable_gdb_stub();
+#endif
 }

/**