[coreboot-gerrit] Change in coreboot[master]: [Test] soc/alderlake/fsp_params.c: Enable DBC

[Anil Kumar K (Code Review)]

Anil Kumar K has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59847 )

Change subject: [Test] soc/alderlake/fsp_params.c: Enable DBC
......................................................................

[Test] soc/alderlake/fsp_params.c: Enable DBC

Change-Id: Id5d6698985b6932c434ef56280c1ef5e5bccad63
---
M src/soc/intel/alderlake/romstage/fsp_params.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/59847/1

diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index 121251e..786b139 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -315,7 +315,7 @@
    	const struct soc_intel_alderlake_config *config)
 {
    /* Set debug probe type */
-	m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_ALDERLAKE_DEBUG_CONSENT;
+	m_cfg->PlatformDebugConsent = 2;

/* CrashLog config */
    m_cfg->CpuCrashLogDevice = CONFIG(SOC_INTEL_CRASHLOG) && is_devfn_enabled(SA_DEVFN_TMT);