Gabe Black (gabeblack@chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3751
-gerrit
commit b4fb5e703cca76324f377d853613565a9f7a3249 Author: Hung-Te Lin hungte@chromium.org Date: Wed Jun 26 19:42:12 2013 +0800
ec/google: Support ChromeOS EC on SPI bus.
For devices with ChromeOS EC on SPI bus, use the standard SPI driver interface (see spi-generic.h) to exchange data.
Note: Only EC protocol v3 is supported for SPI bus.
Change-Id: Ia8dcdecd125a2bd7424d0c7560e046b6d6988a03 Signed-off-by: Hung-Te Lin hungte@chromium.org --- src/ec/google/chromeec/Kconfig | 18 ++++++++-- src/ec/google/chromeec/Makefile.inc | 3 ++ src/ec/google/chromeec/ec_spi.c | 65 +++++++++++++++++++++++++++++++++++++ 3 files changed, 84 insertions(+), 2 deletions(-)
diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig index 1c4a7c0..342db3e 100644 --- a/src/ec/google/chromeec/Kconfig +++ b/src/ec/google/chromeec/Kconfig @@ -22,7 +22,21 @@ config EC_GOOGLE_CHROMEEC_I2C_CHIP
config EC_GOOGLE_CHROMEEC_LPC depends on EC_GOOGLE_CHROMEEC && ARCH_X86 # Needs Plug-and-play. - bool - default y + def_bool y help Google Chrome EC via LPC bus. + +config EC_GOOGLE_CHROMEEC_SPI + depends on EC_GOOGLE_CHROMEEC + def_bool n + help + Google's Chrome EC via SPI bus. + +config EC_GOOGLE_CHROMEEC_SPI_BUS + depends on EC_GOOGLE_CHROMEEC_SPI + hex "SPI bus for Google's Chrome EC" + +config EC_GOOGLE_CHROMEEC_SPI_CHIP + depends on EC_GOOGLE_CHROMEEC_SPI + hex + default 0 diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc index 73b5b5e..541bb13 100644 --- a/src/ec/google/chromeec/Makefile.inc +++ b/src/ec/google/chromeec/Makefile.inc @@ -1,9 +1,12 @@ ramstage-y += ec.c crosec_proto.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c +ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c smm-y += ec.c crosec_proto.c smm-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c smm-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c +smm-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c romstage-y += ec.c crosec_proto.c romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c +romstage-$(CONFIG_EC_GOOGLE_CHROMEEC_SPI) += ec_spi.c diff --git a/src/ec/google/chromeec/ec_spi.c b/src/ec/google/chromeec/ec_spi.c new file mode 100644 index 0000000..5525e31 --- /dev/null +++ b/src/ec/google/chromeec/ec_spi.c @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <spi-generic.h> +#include "ec.h" +#include "ec_commands.h" + +#define CROSEC_SPI_SPEED (500000) + +static int crosec_spi_io(uint8_t *write_bytes, size_t write_size, + uint8_t *read_bytes, size_t read_size, + void *context) +{ + struct spi_slave *slave = (struct spi_slave *)context; + int rv; + + spi_claim_bus(slave); + rv = spi_xfer(slave, write_bytes, write_size * 8, read_bytes, + read_size * 8); + spi_release_bus(slave); + + if (rv != 0) { + printk(BIOS_ERR, "%s: Cannot complete SPI I/O\n", __func__); + return -1; + } + + return 0; +} + +int google_chromeec_command(struct chromeec_command *cec_command) +{ + static struct spi_slave *slave = NULL; + if (!slave) { + slave = spi_setup_slave(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, + CONFIG_EC_GOOGLE_CHROMEEC_SPI_CHIP, + CROSEC_SPI_SPEED, + SPI_READ_FLAG | SPI_WRITE_FLAG); + } + return crosec_command_proto(cec_command, crosec_spi_io, slave); +} + +#ifndef __PRE_RAM__ +u8 google_chromeec_get_event(void) +{ + printk(BIOS_ERR, "%s: Not supported.\n", __func__); + return 0; +} +#endif