[coreboot-gerrit] Change in coreboot[master]: mb/google/zork: Add USB2 phy tuning parameter for SI tuning

[chris wang (Code Review)]

Hello Raul Rangel, Chris Wang, Matt Papageorge,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/42996

to review the following change.

Change subject: mb/google/zork: Add USB2 phy tuning parameter for SI tuning
......................................................................

mb/google/zork: Add USB2 phy tuning parameter for SI tuning

Add the USB2 phy tuning parameter to adjust the USB 2.0 PHY driving strength.

BUG=b:156315391
BRANCH=trembyle-bringup
TEST=Build, verified the tuning value been applied on Trembyle.

Signed-off-by: Chris Wang 
Change-Id: I3d31792d26729e0acb044282c5300886663dde51
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+...
Reviewed-by: Raul E Rangel 
Reviewed-by: Furquan Shaikh 
Reviewed-by: Matt Papageorge 
Tested-by: Matt Papageorge 
---
M src/soc/amd/picasso/chip.h
M src/soc/amd/picasso/fsp_params.c
2 files changed, 41 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/42996/1

diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h
index f5fbe0f..3a6019a 100644
--- a/src/soc/amd/picasso/chip.h
+++ b/src/soc/amd/picasso/chip.h
@@ -14,6 +14,30 @@
 #include <acpi/acpi_device.h>
 #include <arch/smp/mpspec.h>

+/*
+  USB 2.0 PHY Parameters
+*/
+struct usb2_phy_tune {
+	/* Disconnect Threshold Adjustment. Range 0 - 0x7 */
+	uint8_t	com_pds_tune;
+	/* Squelch Threshold Adjustment. Range 0 - 0x7 */
+	uint8_t	sq_rx_tune;
+	/* FS/LS Source Impedance Adjustment. Range 0 - 0xF */
+	uint8_t	tx_fsls_tune;
+	/* HS Transmitter Pre-Emphasis Curent Control. Range 0 - 0x3 */
+	uint8_t	tx_pre_emp_amp_tune;
+	/* HS Transmitter Pre-Emphasis Duration Control. Range: 0 - 0x1 */
+	uint8_t	tx_pre_emp_pulse_tune;
+	/* HS Transmitter Rise/Fall Time Adjustment. Range: 0 - 0x3 */
+	uint8_t	tx_rise_tune;
+	/* HS DC Voltage Level Adjustment. Range 0 - 0xF */
+	uint8_t	rx_vref_tune;
+	/* Transmitter High-Speed Crossover Adjustment. Range 0 - 0x3 */
+	uint8_t	tx_hsxv_tune;
+	/* USB Source Impedance Adjustment. Range 0 - 0x3. */
+	uint8_t	tx_res_tune;
+};
+
 struct soc_amd_picasso_config {
    struct soc_amd_common_config common_config;
    /*
@@ -105,6 +129,14 @@
    } sd_emmc_config;

uint8_t xhci0_force_gen1;
+
+	struct usb2_phy_tune usb_2_port_0_tune_params;
+	struct usb2_phy_tune usb_2_port_1_tune_params;
+	struct usb2_phy_tune usb_2_port_2_tune_params;
+	struct usb2_phy_tune usb_2_port_3_tune_params;
+	struct usb2_phy_tune usb_2_port_4_tune_params;
+	struct usb2_phy_tune usb_2_port_5_tune_params;
+
 };

typedef struct soc_amd_picasso_config config_t;
diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c
index 9decbbf..10bca00 100644
--- a/src/soc/amd/picasso/fsp_params.c
+++ b/src/soc/amd/picasso/fsp_params.c
@@ -98,7 +98,16 @@
 static void fsp_usb_oem_customization(FSP_S_CONFIG *scfg,
    		const struct soc_amd_picasso_config *cfg)
 {
+	size_t num = sizeof(struct usb2_phy_tune);
+
    scfg->xhci0_force_gen1 = cfg->xhci0_force_gen1;
+
+	memcpy(scfg->fch_usb_2_port0_phy_tune, &cfg->usb_2_port_0_tune_params, num);
+	memcpy(scfg->fch_usb_2_port1_phy_tune, &cfg->usb_2_port_1_tune_params, num);
+	memcpy(scfg->fch_usb_2_port2_phy_tune, &cfg->usb_2_port_2_tune_params, num);
+	memcpy(scfg->fch_usb_2_port3_phy_tune, &cfg->usb_2_port_3_tune_params, num);
+	memcpy(scfg->fch_usb_2_port4_phy_tune, &cfg->usb_2_port_4_tune_params, num);
+	memcpy(scfg->fch_usb_2_port5_phy_tune, &cfg->usb_2_port_5_tune_params, num);
 }

void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)