[coreboot-gerrit] Change in coreboot[master]: soc/intel/elkhartlake: Update USB_PORT_MID pin settings

[Werner Zeh (Code Review)]

Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48541 )

Change subject: soc/intel/elkhartlake: Update USB_PORT_MID pin settings
......................................................................

soc/intel/elkhartlake: Update USB_PORT_MID pin settings

Update Pre-emphasis, Transmitter Emphasis & Preemphasis Bias values
for USB_PORT_MID.

Signed-off-by: Tan, Lean Sheng 
Change-Id: I43eeb0fc410197a559df97b340135fac65c00aa5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48541
Reviewed-by: Frans Hendriks 
Reviewed-by: Werner Zeh 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/elkhartlake/include/soc/usb.h
1 file changed, 3 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Werner Zeh: Looks good to me, approved
  Frans Hendriks: Looks good to me, approved

diff --git a/src/soc/intel/elkhartlake/include/soc/usb.h b/src/soc/intel/elkhartlake/include/soc/usb.h
index 247b0ba..3cef823 100644
--- a/src/soc/intel/elkhartlake/include/soc/usb.h
+++ b/src/soc/intel/elkhartlake/include/soc/usb.h
@@ -79,9 +79,9 @@
    .enable        = 1, \
    .ocpin         = (pin), \
    .tx_bias       = USB2_BIAS_0MV, \
-	.tx_emp_enable = USB2_PRE_EMP_ON, \
-	.pre_emp_bias  = USB2_BIAS_56P3MV, \
-	.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP, \
+	.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, \
+	.pre_emp_bias  = USB2_BIAS_45MV, \
+	.pre_emp_bit   = USB2_FULL_BIT_PRE_EMP, \
 }

/* Length = 3"-5.99" */