[coreboot-gerrit] Change in coreboot[master]: nb/intel/sandybridge: Drop write_controller_mr() function

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47486 )

Change subject: nb/intel/sandybridge: Drop write_controller_mr() function
......................................................................

nb/intel/sandybridge: Drop write_controller_mr() function

The only reason to write the MR values to the training result registers
is for EV (Electrical Validation) usage. The hardware doesn't need it.

Change-Id: I808174494729453f4ebcaa13258d735faae68d72
Signed-off-by: Angel Pons 
---
M src/northbridge/intel/sandybridge/raminit_common.c
M src/northbridge/intel/sandybridge/raminit_common.h
M src/northbridge/intel/sandybridge/raminit_native.c
3 files changed, 0 insertions(+), 15 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/47486/1

diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index 60a218b..3fd8cb0 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -4078,18 +4078,6 @@
    }
 }

-void write_controller_mr(ramctr_timing *ctrl)
-{
-	int channel, slotrank;
-
-	FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {
-		MCHBAR32(lane_base[slotrank] + GDCRTRAININGRESULT1(channel)) =
-			make_mr0(ctrl, slotrank);
-		MCHBAR32(lane_base[slotrank] + GDCRTRAININGRESULT2(channel)) =
-			make_mr1(ctrl, slotrank, channel);
-	}
-}
-
 int channel_test(ramctr_timing *ctrl)
 {
    int channel, slotrank, lane;
diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h
index 5b08ce5..a6f4e0b 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.h
+++ b/src/northbridge/intel/sandybridge/raminit_common.h
@@ -244,7 +244,6 @@
 int discover_edges_write(ramctr_timing *ctrl);
 int discover_timC_write(ramctr_timing *ctrl);
 void normalize_training(ramctr_timing *ctrl);
-void write_controller_mr(ramctr_timing *ctrl);
 int channel_test(ramctr_timing *ctrl);
 void set_scrambling_seed(ramctr_timing *ctrl);
 void set_wmm_behavior(const u32 cpu);
diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c
index 844e69a..53017eb 100644
--- a/src/northbridge/intel/sandybridge/raminit_native.c
+++ b/src/northbridge/intel/sandybridge/raminit_native.c
@@ -715,8 +715,6 @@

set_read_write_timings(ctrl);

-	write_controller_mr(ctrl);
-
    if (!s3resume) {
    	err = channel_test(ctrl);
    	if (err)