[coreboot-gerrit] Change in ...coreboot[master]: mb/intel/icelake_rvp: Add SMI handlers

[Aamir Bohra (Code Review)]

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32252

Change subject: mb/intel/icelake_rvp: Add SMI handlers
......................................................................

mb/intel/icelake_rvp: Add SMI handlers

Add SMI handlers for below SMI events:

1. eSPI SMI event.
2. ACPI enable/disable SMI event
   -> Add support for EC to configure SMI mask on ACPI disable.
   -> Add support for EC to configure SCI mask on ACPI enable.
3. Sleep(S3/S5) SMI event
   -> Add support for EC to configure wake mask for S3/S5 event

Change-Id: Ibc0284b99bb2f4807ff2c0ec90b316730b251ddb
Signed-off-by: Aamir Bohra 
---
M src/mainboard/intel/icelake_rvp/Makefile.inc
A src/mainboard/intel/icelake_rvp/smihandler.c
2 files changed, 45 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/32252/1

diff --git a/src/mainboard/intel/icelake_rvp/Makefile.inc b/src/mainboard/intel/icelake_rvp/Makefile.inc
index 7e74f09..ad9100f 100644
--- a/src/mainboard/intel/icelake_rvp/Makefile.inc
+++ b/src/mainboard/intel/icelake_rvp/Makefile.inc
@@ -29,6 +29,8 @@
 ramstage-y += mainboard.c
 ramstage-y += board_id.c

+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+
 subdirs-y += variants/baseboard
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include

diff --git a/src/mainboard/intel/icelake_rvp/smihandler.c b/src/mainboard/intel/icelake_rvp/smihandler.c
new file mode 100644
index 0000000..1ba7dee
--- /dev/null
+++ b/src/mainboard/intel/icelake_rvp/smihandler.c
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/x86/smm.h>
+#include <ec/google/chromeec/smm.h>
+#include <gpio.h>
+#include <soc/gpio.h>
+#include <soc/smm.h>
+#include <variant/ec.h>
+
+#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
+
+void mainboard_smi_espi_handler(void)
+{
+	chromeec_smi_process_events();
+}
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+	chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
+			MAINBOARD_EC_S5_WAKE_EVENTS);
+}
+
+int mainboard_smi_apmc(u8 apmc)
+{
+	chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS,
+			MAINBOARD_EC_SMI_EVENTS);
+	return 0;
+}
+
+#endif
\ No newline at end of file