Arthur Heymans (arthur@aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18549
-gerrit
commit 64eadd843a62faa434c06d7657a2038eda4ee278 Author: Arthur Heymans arthur@aheymans.xyz Date: Thu Mar 2 23:51:09 2017 +0100
nb/intel/i945: Fix PEG port on 945gc
Vendor BIOS leaves UPMC1 untouched (on 945gc the default is 0x0203). Not running PCIEx16 init which is valid for 945gm seems to fix all issues and instabilities related to the PEG port.
According to lspci the link width is at the desired x16. Unknown if devices requesting a lower width work automatically or needs more configuration.
Change-Id: I6da8aa7714073f4b34df5ae3c1eb4c19e27ddc97 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- src/northbridge/intel/i945/early_init.c | 3 ++- src/northbridge/intel/i945/raminit.c | 20 +++++++++++--------- 2 files changed, 13 insertions(+), 10 deletions(-)
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 81a6c83..e7b460b 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -935,7 +935,8 @@ void i945_late_initialization(int s3resume)
i945_setup_dmi_rcrb();
- i945_setup_pci_express_x16(); + if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) + i945_setup_pci_express_x16();
i945_setup_root_complex_topology();
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 8fe5f24..52bb355 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -2524,17 +2524,19 @@ static void sdram_power_management(struct sys_info *sysinfo) reg32 |= (1 << 12) | (1 << 11); MCHBAR32(C1DRC1) = reg32;
- if (i945_silicon_revision()>1) { - /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ - u16 peg_bits = (1 << 5) | (1 << 0); + if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { + if (i945_silicon_revision()>1) { + /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ + u16 peg_bits = (1 << 5) | (1 << 0);
- MCHBAR16(UPMC1) = 0x1010 | peg_bits; - } else { - /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ - u16 peg_bits = (1 << 5) | (1 << 0); + MCHBAR16(UPMC1) = 0x1010 | peg_bits; + } else { + /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ + u16 peg_bits = (1 << 5) | (1 << 0);
- /* Rev 0 and 1 */ - MCHBAR16(UPMC1) = 0x0010 | peg_bits; + /* Rev 0 and 1 */ + MCHBAR16(UPMC1) = 0x0010 | peg_bits; + } }
reg16 = MCHBAR16(UPMC2);