[coreboot-gerrit] Change in coreboot[master]: soc/amd/picasso: Add Upd for support force USB3 to Gen1 by port

[chris wang (Code Review)]

Hello Chris Wang,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/45333

to review the following change.

Change subject: soc/amd/picasso: Add Upd for support force USB3 to Gen1 by port
......................................................................

soc/amd/picasso: Add Upd for support force USB3 to Gen1 by port

add upd usb3_port_force_gen1 for support USB3 port to gen1

BUG=b:167651308
BRANCH=zork
TEST=Build,verify the USB3 speed in gen1

Signed-off-by: Chris Wang 
Change-Id: I896c185988c3ea5dbdd72957b363ebdaa2747cff
---
M src/soc/amd/picasso/chip.h
M src/soc/amd/picasso/fsp_params.c
2 files changed, 2 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/45333/1

diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h
index e3da255..9868220 100644
--- a/src/soc/amd/picasso/chip.h
+++ b/src/soc/amd/picasso/chip.h
@@ -168,7 +168,7 @@
    	USB_OC_PIN_5	= 0x5,
    	USB_OC_NONE	= 0xf,
    } usb_port_overcurrent_pin[USB_PORT_COUNT];
-
+	uint32_t usb3_port_force_gen1;
    /* The array index is the general purpose PCIe clock output number. */
    enum gpp_clk_req_setting gpp_clk_config[GPP_CLK_OUTPUT_COUNT];
 };
diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c
index b21f237..e36ebd0 100644
--- a/src/soc/amd/picasso/fsp_params.c
+++ b/src/soc/amd/picasso/fsp_params.c
@@ -106,6 +106,7 @@
    ASSERT(2 * sizeof(scfg->xhci_oc_pin_select) >= USB_PORT_COUNT);

scfg->xhci0_force_gen1 = cfg->xhci0_force_gen1;
+	scfg->fch_usb_3_port_force_gen1 = cfg->usb3_port_force_gen1;

if (cfg->has_usb2_phy_tune_params) {
    	for (i = 0; i < FSPS_UPD_USB2_PORT_COUNT; i++) {