Vladimir Serbinenko (phcoder@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6920
-gerrit
commit ec71b9e8613cfff1269715c558b3384135592d38 Author: Vladimir Serbinenko phcoder@gmail.com Date: Fri Sep 5 03:37:44 2014 +0200
sandybridge: Move common northbridge finalize to northbridge code.
Change-Id: I6d4178e5aaffc1330b0953b0601bf6b448250a8e Signed-off-by: Vladimir Serbinenko phcoder@gmail.com --- src/mainboard/google/butterfly/romstage.c | 24 +++------------------- src/mainboard/google/link/romstage.c | 24 +++------------------- src/mainboard/google/parrot/romstage.c | 24 +++------------------- src/mainboard/google/stout/romstage.c | 24 +++------------------- src/mainboard/intel/emeraldlake2/romstage.c | 24 +++------------------- src/mainboard/kontron/ktqm77/romstage.c | 24 +++------------------- src/mainboard/lenovo/t520/romstage.c | 24 +++------------------- src/mainboard/lenovo/t530/romstage.c | 22 +------------------- src/mainboard/lenovo/x220/romstage.c | 22 +------------------- src/mainboard/lenovo/x230/romstage.c | 22 +------------------- src/mainboard/samsung/lumpy/romstage.c | 24 ++-------------------- src/mainboard/samsung/stumpy/romstage.c | 24 +++------------------- src/northbridge/intel/sandybridge/early_init.c | 27 +++++++++++++++++++++++++ src/northbridge/intel/sandybridge/sandybridge.h | 1 + 14 files changed, 57 insertions(+), 253 deletions(-)
diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index 083abe1..2227912 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -245,35 +245,17 @@ void main(unsigned long bist) quick_ram_check(); post_code(0x3e);
- MCHBAR16(SSKPD) = 0xCAFE; cbmem_was_initted = !cbmem_recovery(boot_mode==2); if (boot_mode!=2) save_mrc_data(&pei_data);
-#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - - *(u32 *)CBMEM_BOOT_MODE = 0; - *(u32 *)CBMEM_RESUME_BACKUP = 0; - - if ((boot_mode == 2) && cbmem_was_initted) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - if (resume_backup_memory) { - *(u32 *)CBMEM_BOOT_MODE = boot_mode; - *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; - } - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); - } else if (boot_mode == 2) { + if (boot_mode==2 && !cbmem_was_inited) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); hlt(); - } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); } -#endif + northbridge_romstage_finalize(boot_mode==2); + post_code(0x3f); #if CONFIG_CHROMEOS init_chromeos(boot_mode); diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 6d819b4..e13b33f 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -289,35 +289,17 @@ void main(unsigned long bist) quick_ram_check(); post_code(0x3e);
- MCHBAR16(SSKPD) = 0xCAFE; cbmem_was_initted = !cbmem_recovery(boot_mode==2); if (boot_mode!=2) save_mrc_data(&pei_data);
-#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - - *(u32 *)CBMEM_BOOT_MODE = 0; - *(u32 *)CBMEM_RESUME_BACKUP = 0; - - if ((boot_mode == 2) && cbmem_was_initted) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - if (resume_backup_memory) { - *(u32 *)CBMEM_BOOT_MODE = boot_mode; - *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; - } - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); - } else if (boot_mode == 2) { + if (boot_mode==2 && !cbmem_was_inited) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); hlt(); - } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); } -#endif + northbridge_romstage_finalize(boot_mode==2); + post_code(0x3f); #if CONFIG_CHROMEOS init_chromeos(boot_mode); diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index 6c3ec79..d933b47 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -245,35 +245,17 @@ void main(unsigned long bist) quick_ram_check(); post_code(0x3e);
- MCHBAR16(SSKPD) = 0xCAFE; cbmem_was_initted = !cbmem_recovery(boot_mode==2); if (boot_mode!=2) save_mrc_data(&pei_data);
-#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - - *(u32 *)CBMEM_BOOT_MODE = 0; - *(u32 *)CBMEM_RESUME_BACKUP = 0; - - if ((boot_mode == 2) && cbmem_was_initted) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - if (resume_backup_memory) { - *(u32 *)CBMEM_BOOT_MODE = boot_mode; - *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; - } - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); - } else if (boot_mode == 2) { + if (boot_mode==2 && !cbmem_was_inited) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); hlt(); - } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); } -#endif + northbridge_romstage_finalize(boot_mode==2); + post_code(0x3f); #if CONFIG_CHROMEOS init_chromeos(boot_mode); diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index 05caa3e..8a13356 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -299,35 +299,17 @@ void main(unsigned long bist) quick_ram_check(); post_code(0x3e);
- MCHBAR16(SSKPD) = 0xCAFE; cbmem_was_initted = !cbmem_recovery(boot_mode==2); if (boot_mode!=2) save_mrc_data(&pei_data);
-#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - - *(u32 *)CBMEM_BOOT_MODE = 0; - *(u32 *)CBMEM_RESUME_BACKUP = 0; - - if ((boot_mode == 2) && cbmem_was_initted) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - if (resume_backup_memory) { - *(u32 *)CBMEM_BOOT_MODE = boot_mode; - *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; - } - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); - } else if (boot_mode == 2) { + if (boot_mode==2 && !cbmem_was_inited) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); hlt(); - } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); } -#endif + northbridge_romstage_finalize(boot_mode==2); + post_code(0x3f); #if CONFIG_CHROMEOS init_chromeos(boot_mode); diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index e10e7b6..549d767 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -297,35 +297,17 @@ void main(unsigned long bist) quick_ram_check(); post_code(0x3e);
- MCHBAR16(SSKPD) = 0xCAFE; cbmem_was_initted = !cbmem_recovery(boot_mode==2); if (boot_mode!=2) save_mrc_data(&pei_data);
-#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - - *(u32 *)CBMEM_BOOT_MODE = 0; - *(u32 *)CBMEM_RESUME_BACKUP = 0; - - if ((boot_mode == 2) && cbmem_was_initted) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - if (resume_backup_memory) { - *(u32 *)CBMEM_BOOT_MODE = boot_mode; - *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; - } - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); - } else if (boot_mode == 2) { + if (boot_mode==2 && !cbmem_was_inited) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); hlt(); - } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); } -#endif + northbridge_romstage_finalize(boot_mode==2); + post_code(0x3f); #if CONFIG_CHROMEOS init_chromeos(boot_mode); diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index 211bfb5..353488d 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -305,35 +305,17 @@ void main(unsigned long bist) quick_ram_check(); post_code(0x3e);
- MCHBAR16(SSKPD) = 0xCAFE; cbmem_was_initted = !cbmem_recovery(boot_mode==2); if (boot_mode!=2) save_mrc_data(&pei_data);
-#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - - *(u32 *)CBMEM_BOOT_MODE = 0; - *(u32 *)CBMEM_RESUME_BACKUP = 0; - - if ((boot_mode == 2) && cbmem_was_initted) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - if (resume_backup_memory) { - *(u32 *)CBMEM_BOOT_MODE = boot_mode; - *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; - } - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); - } else if (boot_mode == 2) { + if (boot_mode==2 && !cbmem_was_inited) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); hlt(); - } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); } -#endif + northbridge_romstage_finalize(boot_mode==2); + post_code(0x3f); timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c index 8aef922..20c52e6 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/romstage.c @@ -252,36 +252,18 @@ void main(unsigned long bist) quick_ram_check(); post_code(0x3e);
- MCHBAR16(SSKPD) = 0xCAFE; cbmem_was_initted = !cbmem_recovery(boot_mode == 2); if (boot_mode != 2) { save_mrc_data(&pei_data); }
-#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - - *(u32 *)CBMEM_BOOT_MODE = 0; - *(u32 *)CBMEM_RESUME_BACKUP = 0; - - if ((boot_mode == 2) && cbmem_was_initted) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - if (resume_backup_memory) { - *(u32 *)CBMEM_BOOT_MODE = boot_mode; - *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; - } - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); - } else if (boot_mode == 2) { + if (boot_mode==2 && !cbmem_was_inited) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); hlt(); - } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); } -#endif + northbridge_romstage_finalize(boot_mode==2); + post_code(0x3f); timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index c9ad90d..d95f10a 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -240,28 +240,8 @@ void main(unsigned long bist) rcba_config(); post_code(0x3d);
- MCHBAR16(SSKPD) = 0xCAFE; + northbridge_romstage_finalize(s3resume);
-#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - - *(u32 *)CBMEM_BOOT_MODE = 0; - *(u32 *)CBMEM_RESUME_BACKUP = 0; - - if (s3resume) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - if (resume_backup_memory) { - *(u32 *)CBMEM_BOOT_MODE = 2; - *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; - } - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); - } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); - } -#endif post_code(0x3f); timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c index 04d577b..59563f9 100644 --- a/src/mainboard/lenovo/x220/romstage.c +++ b/src/mainboard/lenovo/x220/romstage.c @@ -238,28 +238,8 @@ void main(unsigned long bist) rcba_config(); post_code(0x3d);
- MCHBAR16(SSKPD) = 0xCAFE; + northbridge_romstage_finalize(s3resume);
-#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - - *(u32 *)CBMEM_BOOT_MODE = 0; - *(u32 *)CBMEM_RESUME_BACKUP = 0; - - if (s3resume) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - if (resume_backup_memory) { - *(u32 *)CBMEM_BOOT_MODE = 2; - *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; - } - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); - } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); - } -#endif post_code(0x3f); timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c index 94fa5cf..1a96ab2 100644 --- a/src/mainboard/lenovo/x230/romstage.c +++ b/src/mainboard/lenovo/x230/romstage.c @@ -229,28 +229,8 @@ void main(unsigned long bist) rcba_config(); post_code(0x3d);
- MCHBAR16(SSKPD) = 0xCAFE; + northbridge_romstage_finalize(s3resume);
-#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - - *(u32 *)CBMEM_BOOT_MODE = 0; - *(u32 *)CBMEM_RESUME_BACKUP = 0; - - if (s3resume) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - if (resume_backup_memory) { - *(u32 *)CBMEM_BOOT_MODE = 2; - *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; - } - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); - } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); - } -#endif post_code(0x3f); timestamp_add_now(TS_END_ROMSTAGE); } diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 32f1ec5..20fcaee 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -316,36 +316,16 @@ void main(unsigned long bist) quick_ram_check(); post_code(0x3e);
- MCHBAR16(SSKPD) = 0xCAFE; - cbmem_was_initted = !cbmem_recovery(boot_mode==2); if (boot_mode!=2) save_mrc_data(&pei_data);
-#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - - *(u32 *)CBMEM_BOOT_MODE = 0; - *(u32 *)CBMEM_RESUME_BACKUP = 0; - - if ((boot_mode == 2) && cbmem_was_initted) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - if (resume_backup_memory) { - *(u32 *)CBMEM_BOOT_MODE = boot_mode; - *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; - } - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); - } else if (boot_mode == 2) { + if (boot_mode == 2 && !cbmem_was_initted) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); hlt(); - } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); } -#endif + northbridge_romstage_finalize(boot_mode==2); post_code(0x3f); #if CONFIG_CHROMEOS init_chromeos(boot_mode); diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index a3905ab..9bbbe8d 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -327,35 +327,17 @@ void main(unsigned long bist) quick_ram_check(); post_code(0x3e);
- MCHBAR16(SSKPD) = 0xCAFE; cbmem_was_initted = !cbmem_recovery(boot_mode==2); if (boot_mode!=2) save_mrc_data(&pei_data);
-#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - - *(u32 *)CBMEM_BOOT_MODE = 0; - *(u32 *)CBMEM_RESUME_BACKUP = 0; - - if ((boot_mode == 2) && cbmem_was_initted) { - void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); - if (resume_backup_memory) { - *(u32 *)CBMEM_BOOT_MODE = boot_mode; - *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; - } - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); - } else if (boot_mode == 2) { + if (boot_mode==2 && !cbmem_was_inited) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); hlt(); - } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); } -#endif + northbridge_romstage_finalize(boot_mode==2); + post_code(0x3f); #if CONFIG_CHROMEOS init_chromeos(boot_mode); diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index d1d35db..8bf44c1 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -24,6 +24,7 @@ #include <arch/io.h> #include <device/pci_def.h> #include <elog.h> +#include <cbmem.h> #include <pc80/mc146818rtc.h> #include "sandybridge.h"
@@ -174,3 +175,29 @@ void sandybridge_early_initialization(int chipset_type)
sandybridge_setup_graphics(); } + +void northbridge_romstage_finalize(int s3resume) +{ + MCHBAR16(SSKPD) = 0xCAFE; + +#if CONFIG_HAVE_ACPI_RESUME + /* If there is no high memory area, we didn't boot before, so + * this is not a resume. In that case we just create the cbmem toc. + */ + + *(u32 *)CBMEM_BOOT_MODE = 0; + *(u32 *)CBMEM_RESUME_BACKUP = 0; + + if (s3resume) { + void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + if (resume_backup_memory) { + *(u32 *)CBMEM_BOOT_MODE = 2; + *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; + } + /* Magic for S3 resume */ + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); + } else { + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); + } +#endif +} diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 71a9d2f..c38dfb1 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -209,6 +209,7 @@ void intel_sandybridge_finalize_smm(void); int bridge_silicon_revision(void); void sandybridge_early_initialization(int chipset_type); void sandybridge_late_initialization(void); +void northbridge_romstage_finalize(int s3resume);
/* debugging functions */ void print_pci_devices(void);