[coreboot-gerrit] Change in coreboot[master]: cpu/intel/haswell: Do not set PMG_IO_CAPTURE_BASE MSR

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46917 )

Change subject: cpu/intel/haswell: Do not set PMG_IO_CAPTURE_BASE MSR
......................................................................

cpu/intel/haswell: Do not set PMG_IO_CAPTURE_BASE MSR

This MSR only needs to be programmed when IO MWAIT is to be enabled. The
code came from Sandy Bridge, which already showed this inconsistency.

Change-Id: I424333afd654db9a7e180e9a2c31d369e3d92fd6
Signed-off-by: Angel Pons 
---
M src/cpu/intel/haswell/haswell_init.c
1 file changed, 0 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/46917/1

diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index 21f3f4a..6f483a5 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -452,12 +452,6 @@
    /* The deepest package c-state defaults to factory-configured value. */
    wrmsr(MSR_PKG_CST_CONFIG_CONTROL, msr);

-	msr = rdmsr(MSR_PMG_IO_CAPTURE_BASE);
-	msr.lo &= ~0xffff;
-	msr.lo |= (get_pmbase() + 0x14);	// LVL_2 base address
-	/* The deepest package c-state defaults to factory-configured value. */
-	wrmsr(MSR_PMG_IO_CAPTURE_BASE, msr);
-
    msr = rdmsr(MSR_MISC_PWR_MGMT);
    msr.lo &= ~(1 << 0);	// Enable P-state HW_ALL coordination
    wrmsr(MSR_MISC_PWR_MGMT, msr);