Alexandru Gagniuc (mr.nuke.me@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4762
-gerrit
commit 0911dbe254f004dbc7fbb289a006acb38b691079 Author: Alexandru Gagniuc mr.nuke.me@gmail.com Date: Mon Jan 20 22:26:05 2014 +0100
Revert "Butterfly, Stout: Force SATA link speed to 3 Gbps"
This reverts commit 7b8952c19d8d809b7aeec629b31e1c3d66f19884.
This commit was a hack with no real usefulness, as there is no way to replace the shipping coreboot on a write-protected chromebook. As a result, this change was inconsequential, and only affects people who compile and install coreboot post-mortem.
Also, there was no information as to what the commit was supposed to fix, and as such, it is considered moot.
Change-Id: Ia35f7e8a24f9cb701ce0e357d9b3e929c4e0a4fb Signed-off-by: Alexandru Gagniuc mr.nuke.me@gmail.com --- src/mainboard/google/butterfly/devicetree.cb | 2 -- src/mainboard/google/stout/devicetree.cb | 2 -- 2 files changed, 4 deletions(-)
diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index 9a7a1d5..c797fb0 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -58,8 +58,6 @@ chip northbridge/intel/sandybridge
# Enable SATA ports 0 & 1 register "sata_port_map" = "0x3" - # Set max SATA speed to 3.0 Gb/s - register "sata_interface_speed_support" = "0x2"
# Enable EC Port 0x68/0x6C register "gen1_dec" = "0x00040069" diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 653d3fe..a9e499f 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -58,8 +58,6 @@ chip northbridge/intel/sandybridge register "gpi6_routing" = "2"
register "sata_port_map" = "0x3" - # Set max SATA speed to 3.0 Gb/s - register "sata_interface_speed_support" = "0x2"
# Enable EC Port 0x68/0x6C register "gen1_dec" = "0x00040069"