[coreboot-gerrit] Change in coreboot[master]: sec/intel/txt/ramstage.c: Do not init the heap on S3 resume

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46495 )

Change subject: sec/intel/txt/ramstage.c: Do not init the heap on S3 resume
......................................................................

sec/intel/txt/ramstage.c: Do not init the heap on S3 resume

It causes problems on Haswell: SINIT detects that the heap tables differ
in size, and then issues a Class Code 9, Major Error Code 1 TXT reset.

Change-Id: I26f3d291abc7b2263e0b115e94426ac6ec8e5c48
Signed-off-by: Angel Pons 
---
M src/security/intel/txt/ramstage.c
1 file changed, 3 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/46495/1

diff --git a/src/security/intel/txt/ramstage.c b/src/security/intel/txt/ramstage.c
index 2d56d1f..00e9ce7 100644
--- a/src/security/intel/txt/ramstage.c
+++ b/src/security/intel/txt/ramstage.c
@@ -407,7 +407,9 @@
    write64((void *)TXT_MSEG_SIZE, 0);
    write64((void *)TXT_MSEG_BASE, 0);

-	txt_initialize_heap();
+	/* Only initialize the heap on regular boots */
+	if (!acpi_is_wakeup_s3())
+		txt_initialize_heap();

if (CONFIG(INTEL_TXT_LOGGING))
    	txt_dump_regions();