Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8330
-gerrit
commit 48bd54196f01625981a7d9e423f899fbc533e4b3 Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Wed Jan 28 16:36:28 2015 +0200
pcengines/apu1: Work around a PCI reset issue
This patch is extracted from SAGE release pcengines.apu_139_osp.tar.gz.
To my knowledge there is some yet unidentified power-sequencing issue that causes an incomplete reset on the PCI hardware. Most notably, the Realtek GbE chips fail to read their configuration eeproms and fail to initialise and/or load their MAC address.
Change-Id: Ie5653fce2614066f735e497f835c77d09e8b6b22 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- src/include/reset.h | 6 ++++++ src/southbridge/amd/cimx/sb800/bootblock.c | 18 ++++++++++++++++++ 2 files changed, 24 insertions(+)
diff --git a/src/include/reset.h b/src/include/reset.h index 9430ffe..56f703d 100644 --- a/src/include/reset.h +++ b/src/include/reset.h @@ -10,3 +10,9 @@ void soft_reset(void); void cpu_reset(void);
#endif + +#define PCI_RESET_REGISTER 0xcf9 +#define SYS_RST_BIT (1 << 1) +#define RST_CPU_BIT (1 << 2) +#define PCI_COLD_RESET ( SYS_RST_BIT | RST_CPU_BIT ) +#define PCI_WARM_RESET RST_CPU_BIT diff --git a/src/southbridge/amd/cimx/sb800/bootblock.c b/src/southbridge/amd/cimx/sb800/bootblock.c index 188ba29..c74a0f6 100644 --- a/src/southbridge/amd/cimx/sb800/bootblock.c +++ b/src/southbridge/amd/cimx/sb800/bootblock.c @@ -18,6 +18,7 @@ */
#include <arch/io.h> +#include <reset.h>
static void enable_rom(void) { @@ -111,6 +112,23 @@ static void enable_clocks(void)
static void bootblock_southbridge_init(void) { +#if IS_ENABLED(CONFIG_BOARD_PCENGINES_APU1) + u32 dword; + device_t dev; + + /* Check the value of index 0x44 of BDF 0:14.3. + * A non-zero value indicates that a improper reset + * occurred and that a hard-reset should be performed. + */ + dev = PCI_DEV(0, 0x14, 0x03); + dword = pci_io_read_config32(dev, 0x44); + if (dword != 0x00000000) { + outb(0x00, PCI_RESET_REGISTER); + outb(PCI_COLD_RESET, PCI_RESET_REGISTER); + while(1) ; + } +#endif + /* Setup the rom access for 2M */ enable_rom(); enable_prefetch();