[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Fix comment errors for SMBUS

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/28366

Change subject: soc/intel/cannonlake: Fix comment errors for SMBUS
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soc/intel/cannonlake: Fix comment errors for SMBUS

On CannonLake PCH, SMBUS stays at Bus 0 Device 31 and Function 4,
previous comment in southbridge.asl mention it as Function 3 that was a
mistake.

BUG=N/A
TEST=N/A

Change-Id: I29786457379809b6fcb592e1136ff612539e24dc
Signed-off-by: Lijian Zhao 
---
M src/soc/intel/cannonlake/acpi/southbridge.asl
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/28366/1

diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl
index 4a62485..e4f29b6 100644
--- a/src/soc/intel/cannonlake/acpi/southbridge.asl
+++ b/src/soc/intel/cannonlake/acpi/southbridge.asl
@@ -37,7 +37,7 @@
 /* Serial IO */
 #include "serialio.asl"

-/* SMBus 0:1f.3 */
+/* SMBus 0:1f.4 */
 #include "smbus.asl"

/* USB XHCI 0:14.0 */