Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42450 )
Change subject: nb/intel/sandybridge/gma.c: Add Kconfig options for RC6 and RC6p ......................................................................
nb/intel/sandybridge/gma.c: Add Kconfig options for RC6 and RC6p
Add Kconfig options to enable or disable RC6 and RC6p.
TODO
- Not sure if it's OK to allow to enable RC6p alone without RC6p. If yes then I'll update the patch.
Change-Id: I6166d04b3bcb7a55f1d03c397d87eaa62c64b48b Signed-off-by: Evgeny Zinoviev me@ch1p.io --- M src/northbridge/intel/sandybridge/Kconfig M src/northbridge/intel/sandybridge/gma.c 2 files changed, 26 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/42450/1
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index ef6dc3d..95f1deb 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -129,4 +129,18 @@ config INTEL_GMA_BCLV_OFFSET default 0x48254
+config ENABLE_RC6 + bool "Enable RC6 (Render Standby)" + default y + help + Select this if you want to enable RC6 (Render Standby). + +config ENABLE_RC6P + depends on ENABLE_RC6 + bool "Enable RC6p (Deep Render Standby)" + default n + help + Select this if you want to enable RC6p (Deep Render Standby). + This should only be selected on Ivy Bridge. + endif diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index 8fe2de8..d976530 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -450,15 +450,15 @@ gtt_write(0xa06c, 0x000493e0); /* RP Down EI */ gtt_write(0xa070, 0x0000000a); /* RP Idle Hysteresis */
- /* - * 10a: Enable Render Standby (RC6) - * - * IvyBridge should also support DeepRenderStandby. - * - * Unfortunately it does not work reliably on all SKUs so - * disable it here and it can be enabled by the kernel. - */ - gtt_write(0xa090, 0x88040000); /* HW RC Control */ + /* 10a: Enable Render Standby (RC6) and Deep Render Standby (RC6p) */ + reg32 = 0; +#if CONFIG(ENABLE_RC6) + reg32 |= 0x88040000; +#if CONFIG(ENABLE_RC6P) + reg32 |= 0x00020000; +#endif +#endif + gtt_write(0xa090, reg32);
/* 11: Normal Frequency Request */ /* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 */ @@ -516,8 +516,10 @@ gtt_write(0xa188, gtt_read(0xa188) | 1); }
- /* 16: SW RC Control */ + /* 16: SW RC state: RC6 deepest */ +#if CONFIG(ENABLE_RC6) || CONFIG(ENABLE_RC6P) gtt_write(0xa094, 0x00060000); +#endif
/* Setup Digital Port Hotplug */ reg32 = gtt_read(0xc4030);