[coreboot-gerrit] Change in coreboot[master]: soc/intel/braswell: Increase dcache size

[Shelley Chen (Code Review)]

Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45827 )

Change subject: soc/intel/braswell: Increase dcache size
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Patch Set 2:

(2 comments)

https://review.coreboot.org/c/coreboot/+/45827/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/45827/1//COMMIT_MSG@9 
PS1, Line 9: the
> it?

Done

https://review.coreboot.org/c/coreboot/+/45827/1//COMMIT_MSG@9 
PS1, Line 9: Need to increase the DRAM cache size for braswell as the was getting
           : the compilation error "Cache as RAM area is too full" when moving the
           : mrc_cache writeback to romstage.
> > Increase the DRAM cache size for Braswell to address the […]

Done