[coreboot-gerrit] Change in coreboot[master]: mb/asus/p8h61-m_lx3_r2_0: Extract overridetree

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54387 )

Change subject: mb/asus/p8h61-m_lx3_r2_0: Extract overridetree
......................................................................

mb/asus/p8h61-m_lx3_r2_0: Extract overridetree

Tested with BUILD_TIMELESS=1, coreboot.rom for the Asus P8H61-M LX3 R2.0
remains identical when not adding the .config file in it.

Change-Id: I989f69d000a38a7b1f4e0832341aa347cc0bfe98
Signed-off-by: Angel Pons 
---
M src/mainboard/asus/h61-series/Kconfig
A src/mainboard/asus/h61-series/devicetree.cb
R src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/overridetree.cb
3 files changed, 62 insertions(+), 31 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/54387/1

diff --git a/src/mainboard/asus/h61-series/Kconfig b/src/mainboard/asus/h61-series/Kconfig
index f35cdae..3e802d3 100644
--- a/src/mainboard/asus/h61-series/Kconfig
+++ b/src/mainboard/asus/h61-series/Kconfig
@@ -31,10 +31,22 @@
    default "P8H61-M LX3 R2.0" if BOARD_ASUS_P8H61_M_LX3_R2_0
    default "P8H61-M PRO"      if BOARD_ASUS_P8H61_M_PRO

+# TODO: remove once all boards use overridetrees
+if BOARD_ASUS_P8H61_M_LX3_R2_0
+
+config OVERRIDE_DEVICETREE
+	string
+	default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
+endif
+if !BOARD_ASUS_P8H61_M_LX3_R2_0
+
 config DEVICETREE
    string
    default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"

+endif
+
 config CMOS_DEFAULT_FILE
    default "src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/cmos.default"

diff --git a/src/mainboard/asus/h61-series/devicetree.cb b/src/mainboard/asus/h61-series/devicetree.cb
new file mode 100644
index 0000000..07c0a86
--- /dev/null
+++ b/src/mainboard/asus/h61-series/devicetree.cb
@@ -0,0 +1,50 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/sandybridge
+	device cpu_cluster 0 on
+		chip cpu/intel/model_206ax
+			register "acpi_c1" = "1"
+			register "acpi_c2" = "3"
+			register "acpi_c3" = "5"
+			device lapic 0 on end
+			device lapic 0xacac off end
+		end
+	end
+	device domain 0 on
+		device pci 00.0 on end		# Host bridge
+		device pci 01.0 on end		# PEG
+		device pci 02.0 on end		# iGPU
+
+		chip southbridge/intel/bd82x6x
+			register "c2_latency" = "0x0065"
+			register "sata_port_map" = "0x33"
+			register "spi_lvscc" = "0x2005"
+			register "spi_uvscc" = "0x2005"
+
+			device pci 16.0 on  end		# MEI #1
+			device pci 16.1 off end		# MEI #2
+			device pci 16.2 off end		# ME IDE-R
+			device pci 16.3 off end		# ME KT
+			device pci 19.0 off end		# Intel GbE
+			device pci 1a.0 on  end		# EHCI #2
+			device pci 1b.0 on  end		# HD Audio
+
+			device pci 1c.0 off end		# RP #1
+			device pci 1c.1 off end		# RP #2
+			device pci 1c.2 off end		# RP #3
+			device pci 1c.3 off end		# RP #4
+			device pci 1c.4 off end		# RP #5
+			device pci 1c.5 off end		# RP #6
+			device pci 1c.6 off end		# RP #7
+			device pci 1c.7 off end		# RP #8
+
+			device pci 1d.0 on  end		# EHCI #1
+			device pci 1e.0 off end		# PCI bridge
+			device pci 1f.0 on  end		# LPC bridge
+			device pci 1f.2 on  end		# SATA (AHCI)
+			device pci 1f.3 on  end		# SMBus
+			device pci 1f.5 off end		# SATA (Legacy)
+			device pci 1f.6 off end		# Thermal
+		end
+	end
+end
diff --git a/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/devicetree.cb b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/overridetree.cb
similarity index 64%
rename from src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/devicetree.cb
rename to src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/overridetree.cb
index 1ae77ad..5d9635c 100644
--- a/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/devicetree.cb
+++ b/src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/overridetree.cb
@@ -1,35 +1,10 @@
 ## SPDX-License-Identifier: GPL-2.0-or-later

chip northbridge/intel/sandybridge
-	device cpu_cluster 0 on
-		chip cpu/intel/model_206ax
-			register "acpi_c1" = "1"
-			register "acpi_c2" = "3"
-			register "acpi_c3" = "5"
-			device lapic 0 on end
-			device lapic 0xacac off end
-		end
-	end
    device domain 0 on
    	subsystemid 0x1043 0x844d inherit
-		device pci 00.0 on end		# Host bridge
-		device pci 01.0 on end		# PEG
-		device pci 02.0 on end		# iGPU
-
    	chip southbridge/intel/bd82x6x
-			register "c2_latency" = "0x0065"
    		register "gen1_dec" = "0x000c0291"
-			register "sata_port_map" = "0x33"
-			register "spi_lvscc" = "0x2005"
-			register "spi_uvscc" = "0x2005"
-
-			device pci 16.0 on  end		# MEI #1
-			device pci 16.1 off end		# MEI #2
-			device pci 16.2 off end		# ME IDE-R
-			device pci 16.3 off end		# ME KT
-			device pci 19.0 off end		# Intel GbE
-			device pci 1a.0 on  end		# USB2 EHCI #2
-			device pci 1b.0 on  end		# HD Audio

device pci 1c.0 on  end		# RP #1
    		device pci 1c.1 off end		# RP #2
@@ -40,8 +15,6 @@
    		device pci 1c.6 off end		# RP #7
    		device pci 1c.7 off end		# RP #8

-			device pci 1d.0 on  end		# USB2 EHCI #1
-			device pci 1e.0 off end		# PCI bridge
    		device pci 1f.0 on		# LPC bridge
    			chip superio/nuvoton/nct6779d
    				device pnp 2e.1   off end	# Parallel
@@ -78,10 +51,6 @@
    				device pnp 2e.16  off end	# Deep Sleep
    			end
    		end
-			device pci 1f.2 on  end		# SATA (AHCI)
-			device pci 1f.3 on  end		# SMBus
-			device pci 1f.5 off end		# SATA (Legacy)
-			device pci 1f.6 off end		# Thermal
    	end
    end
 end