[coreboot-gerrit] Change in coreboot[master]: intel/apollolake: Move LPC decode enables to bootblock

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34969 )

Change subject: intel/apollolake: Move LPC decode enables to bootblock
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intel/apollolake: Move LPC decode enables to bootblock

Doing this allows to call console_init() earlier in romstage.
This also fixes IO UART in bootblock, although it appears there
is currently no board that was affected.

Change-Id: Iec363a8c651cc1b05b24229db09d686938118f3a
Signed-off-by: Kyösti Mälkki 
---
M src/soc/intel/apollolake/bootblock/bootblock.c
M src/soc/intel/apollolake/romstage.c
2 files changed, 5 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/34969/1

diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index 7b4eaef..f86c18e 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -21,6 +21,7 @@
 #include <device/pci_ops.h>
 #include <intelblocks/cpulib.h>
 #include <intelblocks/fast_spi.h>
+#include <intelblocks/lpc_lib.h>
 #include <intelblocks/p2sb.h>
 #include <intelblocks/pcr.h>
 #include <intelblocks/rtc.h>
@@ -96,6 +97,8 @@
    /* Prepare UART for serial console. */
    if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))
    	uart_bootblock_init();
+	if (CONFIG(DRIVERS_UART_8250IO))
+		lpc_io_setup_comm_a_b();

if (CONFIG(TPM_ON_FAST_SPI))
    	tpm_enable();
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 3178dbf..1464d2c 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -92,9 +92,6 @@
    /* Enable decoding for HPET. Needed for FSP global pointer storage */
    pci_write_config8(PCH_DEV_P2SB, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 |
    					P2SB_HPTC_ADDRESS_ENABLE);
-
-	if (CONFIG(DRIVERS_UART_8250IO))
-		lpc_io_setup_comm_a_b();
 }

/* Thermal throttle activation offset */
@@ -208,10 +205,10 @@

timestamp_add_now(TS_START_ROMSTAGE);

-	soc_early_romstage_init();
-
    console_init();

+	soc_early_romstage_init();
+
    s3wake = pmc_fill_power_state(ps) == ACPI_S3;
    fsp_memory_init(s3wake);