[coreboot-gerrit] Change in em100[master]: Add more traceable SPI commands

[Stefan Reinauer (Code Review)]

Hello Duncan Laurie,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/em100/+/48584

to review the following change.

Change subject: Add more traceable SPI commands
......................................................................

Add more traceable SPI commands

Some commands always require 4 byte addresses, some require 3 or 2
depending on the mode, and some don't require an address. Adjust
the table accordingly. This is inspired by some code from Duncan.

Signed-off-by: Stefan Reinauer 
Signed-off-by: Duncan Laurie 
Change-Id: I9002253bf6eb7d60c90cdb75492076d5c5c48f21
---
M trace.c
1 file changed, 47 insertions(+), 21 deletions(-)

git pull ssh://review.coreboot.org:29418/em100 refs/changes/84/48584/1

diff --git a/trace.c b/trace.c
index 108691b..46b52b2 100644
--- a/trace.c
+++ b/trace.c
@@ -110,27 +110,49 @@
 };

struct spi_cmd_values spi_command_list[] = {
-		/* name				cmd,	addr,	pad */
-		{"write status register",	0x01,	0,	0},
-		{"page program",		0x02,	1,	0},
-		{"read",			0x03,	1,	0},
-		{"write disable",		0x04,	0,	0},
-		{"read status register",	0x05,	0,	0},
-		{"write enable",		0x06,	0,	0},
-		{"fast read",			0x0b,	1,	1},
-		{"EM100 specific",		0x11,	0,	0},
-		{"fast dual read",		0x3b,	1,	2},
-		{"chip erase",			0x60,	0,	0},
-		{"read JEDEC ID",		0x9f,	0,	0},
-		{"chip erase",			0xc7,	0,	0},
-		{"sector erase",		0xd8,	1,	0},
-		{"enter 4-byte address mode",	0xb7,	0,	0},
-		{"exit 4-byte address mode",	0xe9,	0,	0},
-		{"enter quad i/o mode",		0x35,	0,	0},
-		{"exit quad i/o mode",		0xf5,	0,	0},
-		{"read SFDP Table",		0x5a,	1,	0},
+	/* name                         cmd,    addr,   pad */
+	{"read SFDP",			0x5a,	1,	0},
+	{"write status register",	0x01,	0,	0},
+	{"page program",		0x02,	1,	0},
+	{"read",			0x03,	1,	0},
+	{"write disable",		0x04,	0,	0},
+	{"read status register",	0x05,	0,	0},
+	{"write enable",		0x06,	0,	0},
+	{"fast read",			0x0b,	1,	1},
+	{"EM100 specific",		0x11,	0,	0},
+	{"fast dual read",		0x3b,	1,	2},
+	{"chip erase",			0x60,	0,	0},
+	{"read JEDEC ID",		0x9f,	0,	0},
+	{"chip erase c7h",		0xc7,	0,	0},
+	{"chip erase 60h",		0x60,	0,	0},
+	{"sector erase",		0xd8,	1,	0},
+	{"dual I/O read",		0xbb,	1,	2},
+	{"quad I/O read",		0xeb,	1,	0},
+	{"quad read",			0x6b,	1,	0},
+	{"quad I/O dt read",		0xed,	1,	0},
+	{"quad page program",		0x38,	1,	0},
+	{"sector erase",		0x20,	1,	0},
+	{"block erase 32KB",		0x52,	1,	0},
+	{"block erase 64KB",		0xd8,	1,	0},
+	{"enter 4b mode",		0xb7,	0,	0},
+	{"exit 4b mode",		0xe9,	0,	0},
+	{"read 4b",			0x13,	2,	0},
+	{"fast read 4b",		0x0c,	2,	0},
+	{"dual I/O read 4b",		0xbc,	2,	0},
+	{"dual out read 4b",		0x3c,	2,	0},
+	{"quad I/O read 4b",		0xec,	2,	0},
+	{"quad out read 4b",		0x6c,	2,	0},
+	{"quad I/O dt read 4b",		0xee,	2,	0},
+	{"page program 4b",		0x12,	2,	0},
+	{"quad page program 4b",	0x3e,	2,	0},
+	{"block erase 64KB 4b",		0xdc,	2,	0},
+	{"block erase 32KB 4b",		0x5c,	2,	0},
+	{"sector erase 4b",		0x21,	2,	0},
+	{"enter quad I/O mode",		0x35,	0,	0},
+	{"exit quad I/O mode",		0xf5,	0,	0},

-		{"unknown command",		0xff,	0,	0}
+	{"unknown command",		0xff,   0,	0}
+
 };

static struct spi_cmd_values * get_command_vals(uint8_t command)
@@ -221,13 +243,17 @@
    			if (!spi_cmd_vals->uses_address) {
    				j = 1; /* skip command byte */
    			} else {
+					/* If address_mode > 1 -> always decode 4 bytes */
+					int address_bytes =
+						(spi_cmd_vals->uses_address == 1) ? address_mode : 4;
+
    				if (address_mode == 3)
    					address = (data[i * 8 + 5] << 16) + (data[i * 8 + 6] << 8) + data[i * 8 + 7];
    				else
    					address = (data[i * 8 + 5] << 24) + (data[i * 8 + 6] << 16) + (data[i * 8 + 7] << 8) + data[i * 8 + 8];

/* skip command, address bytes, and padding */
-					j = 1 + address_mode + spi_cmd_vals->pad_bytes;
+					j = 1 + address_bytes + spi_cmd_vals->pad_bytes;
    				if (j > MAX_TRACE_BLOCKLENGTH) {
    					additional_pad_bytes = j -
    						MAX_TRACE_BLOCKLENGTH;