[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Log CSE RO write protection info for ADL

[Sridhar Siricilla (Code Review)]

Attention is currently required from: Tim Wawrzynczak.
Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62987 )

Change subject: soc/intel/alderlake: Log CSE RO write protection info for ADL
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soc/intel/alderlake: Log CSE RO write protection info for ADL

The patch logs write protection information for Alder Lake platform.
As part of write protection informaiton, coreboot logs status on CSE RO
write protection and range. Also, triggers assert if EOM is disabled,
and write protection for CSE RO is not enabled.

TEST=Verify the write protection details on Gimble.

Excerpt from Gimble coreboot log:
    [DEBUG]  ME: WP for RO is enabled        : YES
    [DEBUG]  ME: RO write protection scope - Start=0x1000, End=0x15AFFF

Signed-off-by: Sridhar Siricilla 
Change-Id: I766d5358bb7dd495b4a9b22a2f1b41dc90f3d8d5
---
M src/soc/intel/alderlake/me.c
1 file changed, 17 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/62987/1

diff --git a/src/soc/intel/alderlake/me.c b/src/soc/intel/alderlake/me.c
index ea94902..ce5d3c3 100644
--- a/src/soc/intel/alderlake/me.c
+++ b/src/soc/intel/alderlake/me.c
@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

+#include <assert.h>
 #include <bootstate.h>
 #include <intelblocks/cse.h>
+#include <intelblocks/spi.h>
 #include <console/console.h>
 #include <soc/me.h>
 #include <stdint.h>
@@ -161,6 +163,21 @@
    	hfsts6.fields.cpu_debug_disable ? "YES" : "NO");
    printk(BIOS_DEBUG, "ME: TXT Support                 : %s\n",
    	hfsts6.fields.txt_support ? "YES" : "NO");
+
+	bool cse_ro_wp_en = is_spi_wp_cse_ro_en();
+	printk(BIOS_DEBUG, "ME: WP for RO is enabled        : %s\n",
+		cse_ro_wp_en ? "YES" : "NO");
+
+	if (cse_ro_wp_en) {
+		uint32_t base, limit;
+		spi_get_wp_cse_ro_range(&base, &limit);
+		printk(BIOS_DEBUG, "ME: RO write protection scope - Start=0x%X, End=0x%X\n",
+			base, limit);
+	}
+
+	/* If EOM is disabled, but CSE RO is not write protected, trigger assert */
+	assert(hfsts1.fields.mfg_mode || (!hfsts1.fields.mfg_mode && cse_ro_wp_en));
+
 }

BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_fw_version, NULL);